* "Adam Rappoport" <arappoport(a)amcc.com>:
Is anyone around with verilog background?
Hi Norbert -
Yesterday I registered and logged on to xemacs.org
and submitted (or so
I thought) a bug report for an issue I am having but when I checked the
open issues list I do not see it. That is okay as I didn't hold out much
hope for resolution.
The problem is most likely trivial and I thought I would shoot you an
email as perhaps you would have a quick idea on how to resolve it.
Basically I am using xemacs, version 21.5 and I am building up a design
for an ASIC coded in verilog. I am using several of the verilog
extensions, AUTOINPUT, AUTOOUTPUT, as well as AUTOINST. I am also using
the AUTO_TEMPLATE for wiring at my top level as top level wiring has
different names then the ports. Anyways I find that at the top level
these autos fail and I get a message, buffer to big as xemacs goes
through the auto sequence. Is there any remedy to this?
Any advice or ideas who I may forward this question to would be helpful.
ASIC Designer - AMCC
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