CVS update: MODIFIED: prog-modes, verilog-mode.el ...

User: viteno Date: 05/02/03 20:21:11 Modified: packages/xemacs-packages/prog-modes ChangeLog verilog-mode.el Log: Sync verilog mode with upstream version 4.2. Revision Changes Path 1.225 +4 -0 XEmacs/packages/xemacs-packages/prog-modes/ChangeLog (In the diff below, changes in quantity of whitespace are not shown.) Index: ChangeLog =================================================================== RCS file: /pack/xemacscvs/XEmacs/packages/xemacs-packages/prog-modes/ChangeLog,v retrieving revision 1.224 retrieving revision 1.225 diff -u -b -r1.224 -r1.225 --- ChangeLog 2004/08/17 08:32:54 1.224 +++ ChangeLog 2005/02/03 19:21:10 1.225 ＠＠ -1,3 +1,7 ＠＠ +2005-02-03 Norbert Koch <viteno(a)xemacs.org&gt; + + * verilog-mode.el: Sync with upstream 4.2. + 2004-08-17 Norbert Koch <viteno(a)xemacs.org&gt; * Makefile (VERSION): XEmacs package 2.01 released. 1.8 +1138 -423 XEmacs/packages/xemacs-packages/prog-modes/verilog-mode.el (In the diff below, changes in quantity of whitespace are not shown.) Index: verilog-mode.el =================================================================== RCS file: /pack/xemacscvs/XEmacs/packages/xemacs-packages/prog-modes/verilog-mode.el,v retrieving revision 1.7 retrieving revision 1.8 diff -u -b -r1.7 -r1.8 --- verilog-mode.el 2003/10/29 16:31:41 1.7 +++ verilog-mode.el 2005/02/03 19:21:10 1.8 ＠＠ -1,11 +1,12 ＠＠ ;; verilog-mode.el --- major mode for editing verilog source in Emacs ;; -;; $Id: verilog-mode.el,v 1.5 2002/06/03 02:20:38 youngs Exp $ +;; $Id: verilog-mode.el,v 4.2 2004/12/03 23:05:24 mac Exp $ -;; Copyright (C) 2001 Free Software Foundation, Inc. +;; Copyright (C) 2003 Free Software Foundation, Inc. -;; Author: Michael McNamara (mac(a)surefirev.com) +;; Author: Michael McNamara (mac(a)verilog.com) ;; Senior Vice President of Technology, Verisity Design, Inc. +;; IEEE 1364 Verilog standards committee Chairman ;; (SureFire and Verisity merged October 1999) ;; http://www.verisity.com ;; AUTO features, signal, modsig; by: Wilson Snyder ＠＠ -99,7 +100,7 ＠＠ (provide 'verilog-mode) ;; This variable will always hold the version number of the mode -(defconst verilog-mode-version "$$Revision: 1.5 $$" +(defconst verilog-mode-version "Revision: 4.2" "Version of this verilog mode.") (defconst verilog-running-on-xemacs (string-match "XEmacs" emacs-version)) ＠＠ -152,6 +153,12 ＠＠ nil ;; great (defmacro zmacs-activate-region (&rest args) nil)) (error nil)) + (condition-case nil + (if (fboundp 'char-before) + nil ;; great + (defmacro char-before (&rest body) + (` (char-after (1- (point)))))) + (error nil)) ;; Requires to define variables that would be "free" warnings (condition-case nil (require 'font-lock) ＠＠ -204,13 +211,33 ＠＠ ) )) +(eval-and-compile + (if (fboundp 'regexp-opt) + (defun verilog-regexp-opt (strings &optional paren shy) + (let ((open (if paren "\\(" "")) (close (if paren "\\)" ""))) + (concat open (mapconcat 'regexp-quote strings "\\|") close))) + (if (fboundp 'function-min-args) + (if (= 3 (function-min-args `regexp-opt)) + (defun verilog-regexp-opt (a b) + "Deal with differing number of required arguments for `regexp-opt'. + Call 'regexp-opt' on A and B." + (regexp-opt a b 't)) + (defun verilog-regexp-opt (a b) + "Call 'regexp-opt' on A and B." + (regexp-opt a b)) + ) + (defun verilog-regexp-opt (a b) + "Call 'regexp-opt' on A and B." + (regexp-opt a b)) + ) + )) ;; XEmacs change: workarounds not needed with xemacs-base > 1.81 (eval-when-compile (defalias 'verilog-regexp-opt 'regexp-opt)) (defalias 'verilog-regexp-opt 'regexp-opt) ;(unless (fboundp 'regexp-opt) -; (defun regexp-opt (strings &optional paren shy) +; (defun regexp-opt (strings &optional paren) ; (let ((open (if paren "\\(" "")) (close (if paren "\\)" ""))) ; (concat open (mapconcat 'regexp-quote strings "\\|") close)))) ;(eval-when-compile ＠＠ -429,6 +456,9 ＠＠ (defvar verilog-auto-update-tick nil "Modification tick at which autos were last performed.") +(defvar verilog-auto-last-file-locals nil + "Text from file-local-variables during last evaluation.") + (defvar verilog-error-regexp-add-didit nil) (defvar verilog-error-regexp nil) (setq verilog-error-regexp-add-didit nil ＠＠ -437,19 +467,27 ＠＠ ; SureLint ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2) ; Most SureFire tools - ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), line \\([0-9]+\\):" 2 3 ) + ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 ) ("\ \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5) + ; xsim + ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED] + ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3) ; vcs ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3) ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2) ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3) ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2) + ; Verilator + ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4) + ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4) ; vxl ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3) ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2) + ; Leda + ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2) ) ; "*List of regexps for verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting." ) ＠＠ -472,6 +510,9 ＠＠ ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t) ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t) + ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t) + ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t) + ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t) ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t) ＠＠ -489,14 +530,18 ＠＠ ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t) ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t) + ; Leda + ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t) + ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t) ) "*Keywords to also highlight in Verilog *compilation* buffers." ) (defcustom verilog-library-directories '(".") "*List of directories when looking for files for /*AUTOINST*/. -The directory may be relative to the current file, or absolute. Having at -least the current directory is a good idea. +The directory may be relative to the current file, or absolute. +Environment variables are also expanded in the directory names. +Having at least the current directory is a good idea. You might want these defined in each file; put at the *END* of your file something like: ＠＠ -505,8 +550,9 ＠＠ // verilog-library-directories:(\".\" \"subdir\" \"subdir2\") // End: -Note these are only read when the file is first visited, you must use -\\[find-alternate-file] RET to have these take effect after editing them! +Verilog-mode attempts to detect changes to this local variable, but they +are only insured to be correct when the file is first visited. Thus if you +have problems, use \\[find-alternate-file] RET to have these take effect. See also verilog-library-files and verilog-library-extensions." :group 'verilog-mode-auto ＠＠ -524,8 +570,9 ＠＠ // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\") // End: -Note these are only read when the file is first visited, you must use -\\[find-alternate-file] RET to have these take effect after editing them! +Verilog-mode attempts to detect changes to this local variable, but they +are only insured to be correct when the file is first visited. Thus if you +have problems, use \\[find-alternate-file] RET to have these take effect. See also verilog-library-directories." :group 'verilog-mode-auto ＠＠ -552,14 +599,37 ＠＠ :type 'boolean :group 'verilog-mode-auto) +(defcustom verilog-auto-reset-widths nil + "*If true, AUTORESET should determine the width of signals and use it +to widen the zero (32'h0 for example). This is required by some lint +tools that aren't smart enough to ignore widths of the constant zero. +This is not on my default, as it results in ugly code when parameters +determine the MSB or LSB of a signal inside a AUTORESET." + :type 'boolean + :group 'verilog-mode-auto) + +(defcustom verilog-assignment-delay "" + "*Text used for delayes in delayed assignments. Add a trailing space if set." + :type 'string + :group 'verilog-mode-auto) + (defcustom verilog-auto-inst-vector t "*If true, when creating default ports with AUTOINST, use bus subscripts. If nil, skip the subscript when it matches the entire bus as declared in -the module (AUTOWIRE signals always are subscripted.) Nil may speed up -some simulators, but is less general and harder to read." +the module (AUTOWIRE signals always are subscripted, you must manually +declare the wire to have the subscrips removed.) Nil may speed up some +simulators, but is less general and harder to read, so avoid." :group 'verilog-mode-auto :type 'boolean ) +(defcustom verilog-auto-inst-template-numbers nil + "*If true, when creating templated ports with AUTOINST, add a comment. +The comment will add the line number of the template that was used for that +port declaration. Setting this aids in debugging, but nil is suggested for +regular use to prevent large numbers of merge conflicts." + :group 'verilog-mode-auto + :type 'boolean ) + (defcustom verilog-mode-hook 'verilog-set-compile-command "*Hook (List of functions) run after verilog mode is loaded." :type 'hook ＠＠ -729,6 +799,7 ＠＠ ["AUTOARG" (describe-function 'verilog-auto-arg) t] ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t] ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t] + ["AUTOINOUT" (describe-function 'verilog-auto-inout) t] ["AUTOINPUT" (describe-function 'verilog-auto-input) t] ["AUTOINST" (describe-function 'verilog-auto-inst) t] ["AUTOOUTPUT" (describe-function 'verilog-auto-output) t] ＠＠ -764,7 +835,10 ＠＠ \"(cd /tmp; surecov %s)\". In the former case, the path to the current buffer is concat'ed to the value of verilog-tool; in the later, the path to the current buffer is -substituted for the %s" +substituted for the %s. + +Where __FILE__ appears in the string, the buffer-file-name of the current +buffer, without the directory portion, will be substituted." (interactive) (or (file-exists-p "makefile") ;If there is a makefile, use it (file-exists-p "Makefile") ＠＠ -772,8 +846,20 ＠＠ (setq compile-command (if (string-match "%s" (eval verilog-tool)) (format (eval verilog-tool) (or buffer-file-name "")) - (concat (eval verilog-tool) " " (or buffer-file-name ""))))))) + (concat (eval verilog-tool) " " (or buffer-file-name "")))))) + (verilog-modify-compile-command)) +(defun verilog-modify-compile-command () + "Replace meta-information in compile-command. +Where __FILE__ appears in the string, the buffer-file-name of the current +buffer, without the directory portion, will be substituted." + (when (string-match "\\b__FILE__\\b" compile-command) + (make-local-variable 'compile-command) + (setq compile-command + (verilog-string-replace-matches + "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name)) + t t compile-command)))) + (defun verilog-error-regexp-add () "Add the messages to the `compilation-error-regexp-alist'. Called by `compilation-mode-hook'. This allows \\[next-error] to find the errors." ＠＠ -791,6 +877,25 ＠＠ (add-hook 'compilation-mode-hook 'verilog-error-regexp-add) +(defconst verilog-directive-re + ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif" + ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef" + ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale" + ;; "`time_scale" "`undef" "`while" + "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>") + +(defconst verilog-directive-begin + "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>") + +(defconst verilog-directive-middle + "\\<`\\(else\\|default\\|case\\)\\>") + +(defconst verilog-directive-end + "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>") + +(defconst verilog-directive-re-1 + (concat "[ \t]*" verilog-directive-re)) + ;; ;; Regular expressions used to calculate indent, etc. ;; ＠＠ -804,24 +909,46 ＠＠ ;; b : (defconst verilog-no-indent-begin-re - "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\)\\>") + "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>") (defconst verilog-ends-re (concat - "\\(\\<else\\>\\)\\|" - "\\(\\<if\\>\\)\\|" - "\\(\\<end\\>\\)\\|" - "\\(\\<join\\>\\)\\|" - "\\(\\<endcase\\>\\)\\|" - "\\(\\<endtable\\>\\)\\|" - "\\(\\<endspecify\\>\\)\\|" - "\\(\\<endfunction\\>\\)\\|" - "\\(\\<endtask\\>\\)")) + "\\(\\<else\\>\\)\\|" ; 1 + "\\(\\<if\\>\\)\\|" ; 2 + "\\(\\<end\\>\\)\\|" ; 3 + "\\(\\<endcase\\>\\)\\|" ; 4 + "\\(\\<endfunction\\>\\)\\|" ; 5 + "\\(\\<endtask\\>\\)\\|" ; 6 + "\\(\\<endspecify\\>\\)\\|" ; 7 + "\\(\\<endtable\\>\\)\\|" ; 8 + "\\(\\<endgenerate\\>\\)\\|" ; 9 + "\\(\\<join\\(_any\\|_none\\)?\\>\\)" ; 10 + )) +(defconst verilog-autoindent-lines-re + ;; Matches to names in this list cause auto-end-commentation + ;; + ;; "macromodule" "module" "primitive" "interface" "end" "endcase" "endfunction" + ;; "endtask" "endmodule" "endprimitive" "endinterface" "endspecify" "endtable" "join" + ;; "begin" "else" "`else" "`ifdef" "`endif" "`define" "`undef" "`include" + (concat "\\(" + verilog-directive-re + "\\|\\(\\<begin\\>\\|" + "e\\(lse\\>\\|nd\\(\\>\\|case\\>\\|function\\>\\|module\\>\\|primitive\\>\\|interface\\>\\|package\\>" + "\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)\\)\\|" + "join\\(_any\\|_none\\)?\\>\\|m\\(acromodule\\>\\|odule\\>\\)\\|primitive\\>\\|interface\\>\\|package\\>\\)\\)" )) (defconst verilog-enders-re - (concat "\\(\\<endcase\\>\\)\\|" - "\\(\\<end\\>\\)\\|" - "\\(\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\)\\>\\)")) + (concat "\\(\\<endcase\\>\\)\\|" ; 1 + "\\(\\<end\\>\\)\\|" ; 2 + "\\(\\<end" ; 3, but not used + "\\(" ; 4, but not used + "\\(function\\)\\|" ; 5 + "\\(task\\)\\|" ; 6 + "\\(module\\)\\|" ; 7 + "\\(primitive\\)\\|" ; 8 + "\\(interface\\)\\|" ; 9 + "\\(package\\)" ; 10 + "\\)\\>\\)")) (defconst verilog-endcomment-reason-re (concat "\\(\\<fork\\>\\)\\|" ＠＠ -832,7 +959,13 ＠＠ "\\(\\<task\\>\\)\\|" "\\(\\<function\\>\\)\\|" "\\(\\<initial\\>\\)\\|" + "\\(\\<interface\\>\\)\\|" + "\\(\\<package\\>\\)\\|" + "\\(\\<final\\>\\)\\|" "\\(\\<always\\>\\(\[ \t\]*＠\\)?\\)\\|" + "\\(\\<always_comb\\>\\(\[ \t\]*＠\\)?\\)\\|" + "\\(\\<always_ff\\>\\(\[ \t\]*＠\\)?\\)\\|" + "\\(\\<always_latch\\>\\(\[ \t\]*＠\\)?\\)\\|" "\\(＠\\)\\|" "\\(\\<while\\>\\)\\|" "\\(\\<for\\(ever\\)?\\>\\)\\|" ＠＠ -847,23 +980,23 ＠＠ (defconst verilog-beg-block-re-1 "\\<\\(begin\\)\\|\\(case[xz]?\\)\\|\\(fork\\)\\|\\(table\\)\\|\\(specify\\)\\|\\(function\\)\\|\\(task\\)\\|\\(generate\\)\\>") (defconst verilog-end-block-re - ;; "end" "join" "endcase" "endtable" "endspecify" "endtask" "endfunction" - "\\<\\(end\\(\\>\\|case\\>\\|function\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)\\|join\\>\\)") + ;; "end" "join" "endcase" "endtable" "endspecify" "endtask" "endfunction" "endgenerate" + "\\<\\(end\\(\\>\\|case\\>\\|function\\>\\|generate\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)\\|join\\(_any\\|_none\\)?\\>\\)") -(defconst verilog-end-block-re-1 "\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\>\\)\\|\\(\\<endtable\\>\\)\\|\\(\\<endspecify\\>\\)\\|\\(\\<endfunction\\>\\)\\|\\(\\<endtask\\>\\)") +(defconst verilog-end-block-re-1 "\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\>\\)\\|\\(\\<endtable\\>\\)\\|\\(\\<endspecify\\>\\)\\|\\(\\<endfunction\\>\\)\\|\\(\\<endgenerate\\>\\)\\|\\(\\<endtask\\>\\)") (defconst verilog-declaration-re (eval-when-compile (concat "\\<" (verilog-regexp-opt (list - "assign" "defparam" "event" "inout" "input" "integer" "output" - "parameter" "real" "realtime" "reg" "supply" "supply0" "supply1" - "time" "tri" "tri0" "tri1" "triand" "trior" "trireg" "wand" "wire" - "wor") t ) + "assign" "defparam" "event" "inout" "input" "integer" "localparam" "output" + "parameter" "real" "realtime" "reg" "supply" "supply0" "supply1" "time" + "tri" "tri0" "tri1" "triand" "trior" "trireg" "wand" "wire" "typedef" + "struct" "logic" "bit" "genvar" "wor") t ) "\\>"))) (defconst verilog-range-re "\\[[^]]*\\]") (defconst verilog-macroexp-re "`\\sw+") -(defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^)]*)\\)\\|\\(\\sw+\\)\\)") +(defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^)]*)\\)\\|\\(\\sw+\\)\\)") (defconst verilog-declaration-re-2-no-macro (concat "\\s-*" verilog-declaration-re "\\s-*\\(\\(" verilog-range-re "\\)\\|\\(" verilog-delay-re "\\)" ＠＠ -878,10 +1011,10 ＠＠ (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro)) (defconst verilog-defun-re ;;"module" "macromodule" "primitive" - "\\(\\<\\(m\\(acromodule\\>\\|odule\\>\\)\\|primitive\\>\\)\\)") + "\\(\\<\\(m\\(acromodule\\>\\|odule\\>\\)\\|interface\\>\\|package\\>\\|primitive\\>\\)\\)") (defconst verilog-end-defun-re ;; "endmodule" "endprimitive" -"\\(\\<end\\(module\\>\\|primitive\\>\\)\\)") +"\\(\\<end\\(module\\>\\|primitive\\>\\|interface\\>\\|package\\>\\)\\)") (defconst verilog-zero-indent-re (concat verilog-defun-re "\\|" verilog-end-defun-re)) (defconst verilog-directive-re ＠＠ -912,13 +1045,15 ＠＠ "\\|\\(\\<begin\\>\\|e\\(lse\\>\\|nd\\(\\>\\|case\\>\\|function\\>\\|module\\>\\|primitive\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)\\)\\|join\\>\\|m\\(acromodule\\>\\|odule\\>\\)\\|primitive\\>\\)\\)" )) (defconst verilog-behavioral-block-beg-re - "\\(\\<initial\\>\\|\\<always\\>\\|\\<function\\>\\|\\<task\\>\\)") + (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|" + "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)")) (defconst verilog-indent-reg (concat "\\(\\<begin\\>\\|\\<case[xz]?\\>\\|\\<specify\\>\\|\\<fork\\>\\|\\<table\\>\\)\\|" - "\\(\\<end\\>\\|\\<join\\>\\|\\<endcase\\>\\|\\<endtable\\>\\|\\<endspecify\\>\\)\\|" - "\\(\\<module\\>\\|\\<macromodule\\>\\|\\<primitive\\>\\|\\<initial\\>\\|\\<always\\>\\)\\|" - "\\(\\<endmodule\\>\\|\\<endprimitive\\>\\)\\|" + "\\(\\<end\\>\\|\\<join\\(_any\\|_none\\)?\\>\\|\\<endcase\\>\\|\\<endtable\\>\\|\\<endspecify\\>\\)\\|" + "\\(\\<module\\>\\|\\<macromodule\\>\\|\\<primitive\\>\\|\\<interface\\>\\|\\<package\\>\\|\\<initial\\>\\|\\<final\\>\\|" + "\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|\\<always_latch\\>\\)\\|" + "\\(\\<endmodule\\>\\|\\<endprimitive\\>\\|\\<endinterface\\>\\|\\<endpackage\\>\\)\\|" "\\(\\<generate\\>\\|\\<endgenerate\\>\\)\\|" "\\(\\<endtask\\>\\|\\<endfunction\\>\\)\\|" "\\(\\<function\\>\\|\\<task\\>\\)" ＠＠ -926,21 +1061,24 ＠＠ )) (defconst verilog-indent-re (concat - "\\(\\<\\(always\\>\\|begin\\>\\|case\\(\\>\\|x\\>\\|z\\>\\)\\|end\\(\\>\\|case\\>\\|function\\>\\|module\\>\\|primitive\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)\\|f\\(ork\\>\\|unction\\>\\)\\|initial\\>\\|join\\>\\|m\\(acromodule\\>\\|odule\\>\\)\\|primitive\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)" + "\\(\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\>\\|begin\\>\\|case\\(\\>\\|x\\>\\|z\\>\\)\\|" + "end\\(\\>\\|case\\>\\|function\\>\\|generate\\>\\|module\\>\\|primitive\\>\\|interface\\>\\|package\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)" + "\\|f\\(ork\\>\\|unction\\>\\)\\|generate\\|initial\\>\\|join\\(_any\\|_none\\)?\\>\\|m\\(acromodule\\>\\|odule\\>\\)" + "\\|primitive\\>\\|interface\\>\\|package\\>\\|specify\\>\\|ta\\(ble\\>\\|sk\\>\\)\\)" "\\|" verilog-directive-re "\\)")) (defconst verilog-defun-level-re - ;; "module" "macromodule" "primitive" "initial" "always" "endtask" "endfunction" - "\\(\\<\\(always\\>\\|end\\(function\\>\\|task\\>\\)\\|initial\\>\\|m\\(acromodule\\>\\|odule\\>\\)\\|primitive\\>\\)\\)") + ;; "module" "macromodule" "primitive" "initial" "final" "always" "always_comb" "always_ff" "always_latch" "endtask" "endfunction" + "\\(\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\>\\|end\\(function\\>\\|task\\>\\)\\|final\\|initial\\>\\|m\\(acromodule\\>\\|odule\\>\\)\\|primitive\\>\\|interface\\>\\|package\\>\\)\\)") (defconst verilog-cpp-level-re ;;"endmodule" "endprimitive" - "\\(\\<end\\(module\\>\\|primitive\\>\\)\\)") + "\\(\\<end\\(module\\>\\|primitive\\>\\|interface\\>\\|package\\>\\)\\)") (defconst verilog-behavioral-level-re ;; "function" "task" "\\(\\<\\(function\\>\\|task\\>\\)\\)") (defconst verilog-complete-reg - ;; "always" "initial" "repeat" "case" "casex" "casez" "while" "if" "for" "forever" "else" - "\\<\\(always\\|case\\(\\|[xz]\\)\\|begin\\|else\\|generate\\|for\\(\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>") + ;; "always" "always_latch" "always_ff" "always_comb" "initial" "final" "repeat" "case" "casex" "casez" "while" "if" "for" "forever" "else" "parameter" + "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|begin\\|else\\|generate\\|for\\(\\|ever\\)\\|final\\|i\\(f\\|nitial\\)\\|parameter\\|repeat\\|while\\)\\>") (defconst verilog-end-statement-re (concat "\\(" verilog-beg-block-re "\\)\\|\\(" verilog-end-block-re "\\)")) ＠＠ -954,19 +1092,43 ＠＠ (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */") (defconst verilog-keywords - '("`define" "`else" "`endif" "`ifdef" "`include" "`timescale" - "`undef" "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" - "case" "casex" "casez" "cmos" "default" "defparam" "disable" "else" "end" - "endcase" "endfunction" "endgenerate" "endmodule" "endprimitive" - "endspecify" "endtable" "endtask" "event" "for" "force" "forever" - "fork" "function" "generate" "if" "initial" "inout" "input" "integer" - "join" "macromodule" "makefile" "module" "nand" "negedge" "nmos" "nor" - "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" - "primitive" "pulldown" "pullup" "rcmos" "real" "realtime" "reg" - "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "signed" - "specify" "supply" "supply0" "supply1" "table" "task" "time" "tran" - "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" - "vectored" "wait" "wand" "while" "wire" "wor" "xnor" "xor" ) + '( "`define" "`else" "`endif" "`ifdef" + "`include" "`timescale" "`undef" + "alias" "always" "always_comb" "always_ff" "always_latch" "and" + "assert" "assign" "assume" "automatic" "before" "begin" "bind" + "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte" + "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos" + "config" "const" "constraint" "context" "continue" "cover" + "covergroup" "coverpoint" "cross" "deassign" "default" "defparam" + "design" "disable" "dist" "do" "edge" "else" "end" "endcase" + "endclass" "endclocking" "endconfig" "endfunction" "endgenerate" + "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive" + "endprogram" "endproperty" "endspecify" "endsequence" "endtable" + "endtask" "enum" "event" "expect" "export" "extends" "extern" + "final" "first_match" "for" "force" "foreach" "forever" "fork" + "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if" + "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir" + "include" "initial" "inout" "input" "inside" "instance" "int" + "integer" "interface" "intersect" "join" "join_any" "join_none" + "large" "liblist" "library" "local" "localparam" "logic" + "longint" "macromodule" "matches" "medium" "modport" "module" + "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not" + "notif0" "notif1" "null" "or" "output" "package" "packed" + "parameter" "pmos" "posedge" "primitive" "priority" "program" + "property" "protected" "pull0" "pull1" "pulldown" "pullup" + "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" + "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg" + "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0" + "rtranif1" "scalared" "sequence" "shortint" "shortreal" + "showcancelled" "signed" "small" "solve" "specify" "specparam" + "static" "string" "strong0" "strong1" "struct" "super" "supply0" + "supply1" "table" "tagged" "task" "this" "throughout" "time" + "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri" + "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union" + "unique" "unsigned" "use" "var" "vectored" "virtual" "void" + "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard" + "wire" "with" "within" "wor" "xnor" "xor" + ) "List of Verilog keywords.") ＠＠ -1153,13 +1315,35 ＠＠ "Font lock mode face used to background highlight translate-off regions." :group 'font-lock-highlighting-faces) +(defvar + verilog-font-lock-p1800-face + 'verilog-font-lock-p1800-face + "Font to use for p1800 keywords") +(defface verilog-font-p1800-face + '((((class color) + (background light)) + (:foreground "DarkOrange3" :bold t )) + (((class color) + (background dark)) + (:foreground "gray10" :bold t )) + (t (:italic t))) + "Font lock mode face used to highlight P1800 keywords." + :group 'font-lock-highlighting-faces) + (let* ((verilog-type-font-keywords (eval-when-compile (verilog-regexp-opt - '("defparam" "event" "inout" "input" "integer" "output" "parameter" - "real" "realtime" "reg" "signed" "supply" "supply0" "supply1" "time" - "tri" "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wand" "wire" - "wor" ) nil ))) + '( + "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam" + "event" "genvar" "inout" "input" "integer" "localparam" + "logic" "nand" "nmos" "not" "notif0" "notif1" "or" + "output" "parameter" "pmos" "pull0" "pull1" "pullup" + "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" + "rtranif0" "rtranif1" "signed" "struct" "supply" + "supply0" "supply1" "time" "tran" "tranif0" "tranif1" + "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef" + "vectored" "wand" "wire" "wor" "xnor" "xor" + ) nil ))) (verilog-pragma-keywords (eval-when-compile ＠＠ -1167,15 +1351,46 ＠＠ '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil ))) + (verilog-p1800-keywords + (eval-when-compile + (verilog-regexp-opt + '("alias" "assert" "assume" "automatic" "before" "bind" + "bins" "binsof" "break" "byte" "cell" "chandle" "class" + "clocking" "config" "const" "constraint" "context" "continue" + "cover" "covergroup" "coverpoint" "cross" "deassign" "design" + "dist" "do" "edge" "endclass" "endclocking" "endconfig" + "endgroup" "endprogram" "endproperty" "endsequence" "enum" + "expect" "export" "extends" "extern" "first_match" "foreach" + "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins" + "illegal_bins" "import" "incdir" "include" "inside" "instance" + "int" "intersect" "large" "liblist" "library" "local" "longint" + "matches" "medium" "modport" "new" "noshowcancelled" "null" + "packed" "program" "property" "protected" "pull0" "pull1" + "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" + "randcase" "randsequence" "ref" "release" "return" "scalared" + "sequence" "shortint" "shortreal" "showcancelled" "small" "solve" + "specparam" "static" "string" "strong0" "strong1" "struct" + "super" "tagged" "this" "throughout" "timeprecision" "timeunit" + "type" "union" "unsigned" "use" "var" "virtual" "void" + "wait_order" "weak0" "weak1" "wildcard" "with" "within" + ) nil ))) + + (verilog-font-keywords (eval-when-compile (verilog-regexp-opt - '( "always" "assign" "begin" "case" "casex" "casez" "default" "deassign" - "disable" "else" "end" "endcase" "endfunction" "endgenerate" "endmodule" - "endprimitive" "endspecify" "endtable" "endtask" "for" "force" - "forever" "fork" "function" "generate" "if" "initial" "join" "macromodule" - "module" "negedge" "posedge" "primitive" "repeat" "release" "specify" - "table" "task" "wait" "while" ) nil )))) + '( + "assign" "begin" "case" "casex" "casez" "deassign" + "default" "disable" "else" "end" "endcase" "endfunction" + "endgenerate" "endinterface" "endmodule" "endprimitive" + "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break" "continue" + "forever" "fork" "function" "generate" "if" "iff" "initial" + "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge" + "package" "endpackage" "always" "always_comb" "always_ff" + "always_latch" "posedge" "primitive" "priority" "release" + "repeat" "specify" "table" "task" "unique" "wait" "while" + + ) nil )))) (setq verilog-font-lock-keywords (list ＠＠ -1187,6 +1402,10 ＠＠ ;; Fontify all types (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>") 'font-lock-type-face) + ;; Fontify IEEE-P1800 keywords + (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>") + 'verilog-font-p1800-face) + )) (setq verilog-font-lock-keywords-1 ＠＠ -1194,7 +1413,7 ＠＠ (list ;; Fontify module definitions (list - "\\<\\(\\(macro\\)?module\\|primitive\\|task\\)\\>\\s-*\\(\\sw+\\)" + "\\<\\(\\(macro\\)?module\\|primitive\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)" '(1 font-lock-keyword-face) '(3 font-lock-function-name-face 'prepend)) ;; Fontify function definitions ＠＠ -1221,7 +1440,7 ＠＠ ;; Fontify macro definitions/ uses '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 font-lock-function-name-face) ;; Fontify delays/numbers - '("\\(＠\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^)]+)\\|\\sw+\\)\\)\\)" + '("\\(＠\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^)]+)\\|\\sw+\\)\\)\\)" 0 font-lock-type-face append) ))) ＠＠ -1399,12 +1618,16 ＠＠ ) ((looking-at verilog-end-block-re) (verilog-leap-to-head)) - ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)") + ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)") (cond ((match-end 1) (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move)) ((match-end 2) (verilog-re-search-backward "\\<primitive\\>" nil 'move)) + ((match-end 3) + (verilog-re-search-backward "\\<interface\\>" nil 'move)) + ((match-end 4) + (verilog-re-search-backward "\\<package\\>" nil 'move)) (t (goto-char st) (backward-sexp 1)))) ＠＠ -1433,7 +1656,7 ＠＠ (setq reg "\\(\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) ((match-end 3) ; join ;; Search forward for matching fork - (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\>\\)" )) + (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) ((match-end 4) ; endtable ;; Search forward for matching table (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) ＠＠ -1463,12 +1686,16 ＠＠ (setq nest (1+ nest))))) ))) ) - ((looking-at "\\(\\<\\(macro\\)?module\\>\\)\\|\\(\\<primitive\\>\\)") + ((looking-at "\\(\\<\\(macro\\)?module\\>\\)\\|\\(\\<primitive\\>\\)\\|\\<interface\\>\\)\\|\\(\\<package\\>\\)") (cond ((match-end 1) (verilog-re-search-forward "\\<endmodule\\>" nil 'move)) ((match-end 2) (verilog-re-search-forward "\\<endprimitive\\>" nil 'move)) + ((match-end 3) + (verilog-re-search-forward "\\<endinterface\\>" nil 'move)) + ((match-end 4) + (verilog-re-search-forward "\\<endpackage\\>" nil 'move)) (t (goto-char st) (if (= (following-char) ?\) ) ＠＠ -1632,6 +1859,7 ＠＠ \\[verilog-sk-fork] Insert a fork begin .. end .. join block \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block +\\[verilog-sk-interface] Insert an interface .. (.. );.. endinterface block \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block \\[verilog-sk-specify] Insert a specify .. endspecify block \\[verilog-sk-task] Insert a task .. begin .. end endtask block ＠＠ -1677,6 +1905,8 ＠＠ (setq verilog-which-tool 1) (setq verilog-tool 'verilog-linter) (verilog-set-compile-command) + (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables + (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t)) ;; Setting up things for font-lock (if verilog-running-on-xemacs ＠＠ -1688,11 +1918,22 ＠＠ (add-submenu nil verilog-xemacs-menu))) )) ;; Stuff for GNU emacs (make-local-variable 'font-lock-defaults) + ;;------------------------------------------------------------ + ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el) + ;; all buffer local: + (make-local-hook 'font-lock-mode-hook) + (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20 + (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t) + (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20 + (make-local-hook 'after-change-functions) + (add-hook 'after-change-functions 'verilog-colorize-include-files t t) + ;; Tell imenu how to handle verilog. (make-local-variable 'imenu-generic-expression) (setq imenu-generic-expression verilog-imenu-generic-expression) ;; Stuff for autos (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local + (verilog-auto-reeval-locals t) ; Save locals in case user changes them (run-hooks 'verilog-mode-hook))  ＠＠ -1868,6 +2109,13 ＠＠ ;; ;; Interactive functions ;; + +(defun verilog-indent-buffer () + "Indent-region the entire buffer as Verilog code." + (interactive) + (verilog-mode) + (indent-region (point-min) (point-max) nil)) + (defun verilog-insert-block () "Insert Verilog begin ... end; block in the code with right indentation." (interactive) ＠＠ -1909,7 +2157,7 ＠＠ a = b a[ 7] = b a = b a[ 8] = b" - (interactive "MAX?") + (interactive "NMAX?") (save-excursion (let ((n 0)) (while (< n MAX) ＠＠ -2075,8 +2323,7 ＠＠ (> (marker-position e) (point)) (verilog-re-search-forward (concat - "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|" - "\\(primitive\\)\\|\\(case\\)\\)?\\>" + "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>" "\\|\\(`endif\\)\\|\\(`else\\)") nil 'move)) (goto-char (match-beginning 0)) ＠＠ -2208,7 +2455,7 ＠＠ (save-excursion (while (and (/= nest 0) - (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\)\\>" lim 'move) + (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move) (cond ((match-end 1) ; fork (setq nest (1- nest))) ＠＠ -2314,7 +2561,7 ＠＠ Insert `// case: 7 ' or `// NAME ' on this line if appropriate. Insert `// case expr ' if this line ends a case block. Insert `// ifdef FOO ' if this line ends code conditional on FOO. -Insert `// NAME ' if this line ends a module or primitive named NAME." +Insert `// NAME ' if this line ends a function, task, module, primitive or interface named NAME." (save-excursion (cond (; Comment close preprocessor directives ＠＠ -2377,13 +2624,12 ＠＠ (end-of-line) (search-backward "//" (verilog-get-beg-of-line) t))))) (let ((type (car indent-str))) - (if (eq type 'declaration) - () - (if - (looking-at verilog-enders-re) + (unless (eq type 'declaration) + (unless (looking-at (concat "\\(" verilog-enders-re "\\)[ \t]*:")) ;; ignore named ends + (if (looking-at verilog-enders-re) (cond (;- This is a case block; search back for the start of this case - (match-end 1) + (match-end 1) ;; of verilog-enders-re (let ((err 't) (str "UNMATCHED!!")) ＠＠ -2404,7 +2650,7 ＠＠ )) (;- This is a begin..end block - (match-end 2) + (match-end 2) ;; of verilog-enders-re (let ((str " // UNMATCHED !!") (err 't) (here (point)) ＠＠ -2568,7 +2814,7 ＠＠ (if err (ding 't)) )))) - (;- this is end{function,task,module} + (;- this is end{function,generate,task,module,primative,table,generate} t (let (string reg (width nil)) (end-of-line) ＠＠ -2578,16 +2824,20 ＠＠ (delete-horizontal-space) (backward-sexp) (cond - ((match-end 5) + ((match-end 5) ;; of verilog-enders-re (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)") (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?") ) - ((match-end 6) + ((match-end 6) ;; of verilog-enders-re (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")) - ((match-end 7) + ((match-end 7) ;; of verilog-enders-re (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>")) - ((match-end 8) - (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|function\\|task\\|\\(macro\\)?module\\)\\>\\)")) + ((match-end 8) ;; of verilog-enders-re + (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)")) + ((match-end 9) ;; of verilog-enders-re + (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)")) + ((match-end 10) ;; of verilog-enders-re + (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) ) (let (b e) (save-excursion ＠＠ -2609,10 +2859,10 ＠＠ (setq string (buffer-substring b e))) (t (ding 't) - (setq string "unmatched end(function|task|module|primitive)"))))) + (setq string "unmatched end(function|task|module|primitive|interface|package)"))))) (end-of-line) (insert (concat " // " string ))) - ))))))))) + )))))))))) (defun verilog-get-expr() "Grab expression at point, e.g, case ( a | b & (c ^d))" ＠＠ -2960,7 +3210,7 ＠＠ (cond ((match-end 1) ; else, we're in deep (setq elsec (1+ elsec))) - ((match-end 2) ; found it + ((match-end 2) ; if (setq elsec (1- elsec)) (if (= 0 elsec) (if verilog-align-ifelse ＠＠ -2973,30 +3223,33 ＠＠ ; try to leap back to matching outward block by striding across ; indent level changing tokens then immediately ; previous line governs indentation. - (let ((reg)(nest 1)) -;; verilog-ends => else|if|end|join|endcase|endtable|endspecify|endfunction|endtask + (let (( reg) (nest 1)) +;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endtable|endspecify|endfunction|endtask|endgenerate (cond ((match-end 3) ; end ;; Search back for matching begin (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" )) - ((match-end 5) ; endcase + ((match-end 4) ; endcase ;; Search back for matching case (setq reg "\\(\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) - ((match-end 7) ; endspecify - ;; Search back for matching specify - (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) - ((match-end 8) ; endfunction + ((match-end 5) ; endfunction ;; Search back for matching function (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) - ((match-end 9) ; endtask + ((match-end 6) ; endtask ;; Search back for matching task (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) - ((match-end 4) ; join - ;; Search back for matching fork - (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\>\\)" )) - ((match-end 6) ; endtable + ((match-end 7) ; endspecify + ;; Search back for matching specify + (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) + ((match-end 8) ; endtable ;; Search back for matching table (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) + ((match-end 9) ; endgenerate + ;; Search back for matching generate + (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) + ((match-end 10) ; join + ;; Search back for matching fork + (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" )) ) (catch 'skip (while (verilog-re-search-backward reg nil 'move) ＠＠ -3114,14 +3367,14 ＠＠ ((looking-at "\\<end\\>") ;; Search back for matching begin (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|" - "\\(\\<endcase\\>\\)\\|\\(\\<join\\>\\)" ))) + "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))) ((looking-at "\\<endcase\\>") ;; Search back for matching case (setq reg "\\(\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" )) - ((looking-at "\\<join\\>") + ((looking-at "\\<join\\(_any\\|_none\\)?\\>") ;; Search back for matching fork - (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\>\\)" )) + (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) ((looking-at "\\<endtable\\>") ;; Search back for matching table (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) ＠＠ -3131,6 +3384,9 ＠＠ ((looking-at "\\<endfunction\\>") ;; Search back for matching function (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) + ((looking-at "\\<endgenerate\\>") + ;; Search back for matching generate + (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) ((looking-at "\\<endtask\\>") ;; Search back for matching task (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) ＠＠ -3160,7 +3416,7 ＠＠ (setq snest nest) (setq nest (1+ nest)) (setq sreg reg) - (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\>\\)" )) + (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) )))))) (defun verilog-continued-line () ＠＠ -3194,6 +3450,9 ＠＠ nil) (;-- Could be 'case (foo)' or 'always ＠(bar)' which is complete ; also could be simply '＠(foo)' + ; or foo u1 #(a=8) + ; (b, ... which ISN'T complete + ;;;; Do we need this??? (= (preceding-char) ?\)) (progn (backward-char) ＠＠ -3202,23 +3461,26 ＠＠ (let ((back (point))) (forward-word -1) (cond - ((looking-at "\\<\\(always\\|case\\(\\|[xz]\\)\\|for\\(\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>") + ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>") (not (looking-at "\\<case[xz]?\\>[^:]"))) (t (goto-char back) - (if (= (preceding-char) ?\＠) - (progn (backward-char) + (cond + ((= (preceding-char) ?\＠) + (backward-char) (save-excursion (verilog-backward-token) - (not (looking-at "\\<\\(always\\|initial\\|while\\)\\>")))) - nil)) - )))) + (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>")))) + ((= (preceding-char) ?\#) + t) + (t t)) + ))))) (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete t (forward-word -1) (cond - ((looking-at "\\(else\\)\\|\\(initial\\>\\)\\|\\(always\\>\\)") + ((looking-at "\\(else\\)\\|\\(initial\\>\\)\\|\\(always\\(_latch\\|_ff\\|_comb\\)?\\>\\)") t) ((looking-at verilog-indent-reg) nil) ＠＠ -4026,16 +4288,19 ＠＠ (defvar verilog-type-keywords - '("and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input" - "integer" "nand" "nmos" "nor" "not" "notif0" "notif1" "or" "output" "parameter" - "pmos" "pull0" "pull1" "pullup" "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" - "rtranif0" "rtranif1" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" - "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor" ) + '( + "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input" + "integer" "localparam" "logic" "nand" "nmos" "nor" "not" "notif0" + "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup" + "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0" + "rtranif1" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" + "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor" + ) "*Keywords for types used when completing a word in a declaration or parmlist. \(eg. integer, real, reg...)") (defvar verilog-cpp-keywords - '("module" "macromodule" "primitive" "timescale" "define" "ifdef" + '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else" "endif") "*Keywords to complete when at first word of a line in declarative scope. \(eg. initial, always, begin, assign.) ＠＠ -4044,8 +4309,12 ＠＠ (defvar verilog-defun-keywords (append - '("begin" "function" "task" "initial" "always" "assign" - "endmodule" "specify" "endspecify" "generate" "endgenerate") + '( + "always" "always_comb" "always_ff" "always_latch" "assign" + "begin" "end" "generate" "endgenerate" "module" "endmodule" + "specify" "endspecify" "function" "endfunction" "initial" "final" + "task" "endtask" "primitive" "endprimitive" + ) verilog-type-keywords) "*Keywords to complete when at first word of a line in declarative scope. \(eg. initial, always, begin, assign.) ＠＠ -4053,22 +4322,25 ＠＠ will be completed runtime and should not be added to this list.") (defvar verilog-block-keywords - '("begin" "fork" "join" "case" "end" "if" "else" "for" "while" "repeat" - "endgenerate" "endspecify" "endfunction" "endtask") + '( + "begin" "break" "case" "continue" "else" "end" "endfunction" + "endgenerate" "endinterface" "endpackage" "endspecify" "endtask" + "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return" + "while") "*Keywords to complete when at first word of a line in behavioral scope. \(eg. begin, if, then, else, for, fork.) The procedures and variables defined within the Verilog program will be completed runtime and should not be added to this list.") (defvar verilog-tf-keywords - '("begin" "fork" "join" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat") + '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat") "*Keywords to complete when at first word of a line in a task or function. \(eg. begin, if, then, else, for, fork.) The procedures and variables defined within the Verilog program will be completed runtime and should not be added to this list.") (defvar verilog-case-keywords - '("begin" "fork" "join" "case" "end" "endcase" "if" "else" "for" "repeat") + '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat") "*Keywords to complete when at first word of a line in case scope. \(eg. begin, if, then, else, for, fork.) The procedures and variables defined within the Verilog program ＠＠ -4208,6 +4480,11 ＠＠ (verilog-func-completion 'module) (verilog-keyword-completion verilog-defun-keywords)) + ((eq state 'behavioral) + (save-excursion (verilog-var-completion)) + (verilog-func-completion 'module) + (verilog-keyword-completion verilog-defun-keywords)) + ((eq state 'block) (save-excursion (verilog-var-completion)) (verilog-func-completion 'tf) ＠＠ -4666,6 +4943,59 ＠＠ ;; Signal list parsing ;; +(defsubst verilog-modi-get-decls (modi) + (verilog-modi-cache-results modi 'verilog-read-decls)) + +(defsubst verilog-modi-get-sub-decls (modi) + (verilog-modi-cache-results modi 'verilog-read-sub-decls)) + +;; Signal reading for given module +;; Note these all take modi's - as returned from the verilog-modi-current function +(defsubst verilog-modi-get-outputs (modi) + (aref (verilog-modi-get-decls modi) 0)) +(defsubst verilog-modi-get-inouts (modi) + (aref (verilog-modi-get-decls modi) 1)) +(defsubst verilog-modi-get-inputs (modi) + (aref (verilog-modi-get-decls modi) 2)) +(defsubst verilog-modi-get-wires (modi) + (aref (verilog-modi-get-decls modi) 3)) +(defsubst verilog-modi-get-regs (modi) + (aref (verilog-modi-get-decls modi) 4)) +(defsubst verilog-modi-get-assigns (modi) + (aref (verilog-modi-get-decls modi) 5)) +(defsubst verilog-modi-get-consts (modi) + (aref (verilog-modi-get-decls modi) 6)) +(defsubst verilog-modi-get-sub-outputs (modi) + (aref (verilog-modi-get-sub-decls modi) 0)) +(defsubst verilog-modi-get-sub-inouts (modi) + (aref (verilog-modi-get-sub-decls modi) 1)) +(defsubst verilog-modi-get-sub-inputs (modi) + (aref (verilog-modi-get-sub-decls modi) 2)) + +;; Elements of a signal list +(defsubst verilog-sig-name (sig) + (car sig)) +(defsubst verilog-sig-bits (sig) + (nth 1 sig)) +(defsubst verilog-sig-comment (sig) + (nth 2 sig)) +(defsubst verilog-sig-memory (sig) + (nth 3 sig)) +(defsubst verilog-sig-enum (sig) + (nth 4 sig)) +(defsubst verilog-sig-signed (sig) + (nth 5 sig)) +(defsubst verilog-sig-width (sig) + (verilog-make-width-expression (verilog-sig-bits sig))) + +(defsubst verilog-alw-get-inputs (sigs) + (nth 2 sigs)) +(defsubst verilog-alw-get-outputs (sigs) + (nth 0 sigs)) +(defsubst verilog-alw-get-uses-delayed (sigs) + (nth 3 sigs)) + + (defun verilog-signals-not-in (in-list not-list) "Return list of signals in IN-LIST that aren't also in NOT-LIST. Signals must be in standard (base vector) form." ＠＠ -4702,17 +5032,42 ＠＠ "Compare signal A and B for sorting." (string< (car a) (car b))) +(defun verilog-signals-not-params (in-list) + "Return list of signals in IN-LIST that aren't parameters or +numeric constants." + (let (out-list) + (while in-list + (unless (boundp (intern (concat "vh-" (car (car in-list))))) + (setq out-list (cons (car in-list) out-list))) + (setq in-list (cdr in-list))) + (nreverse out-list))) + (defun verilog-signals-combine-bus (in-list) "Return a list of signals in IN-LIST, with busses combined. Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]." - (let ((combo "") - out-list signal highbit lowbit svhighbit svlowbit comment svbusstring bus) + (let (combo + out-list + sig highbit lowbit ; Temp information about current signal + sv-name sv-highbit sv-lowbit ; Details about signal we are forming + sv-comment sv-memory sv-enum sv-signed sv-busstring + bus) ;; Shove signals so duplicated signals will be adjacent (setq in-list (sort in-list `verilog-signals-sort-compare)) (while in-list - (setq signal (nth 0 (car in-list)) - bus (nth 1 (car in-list)) - comment (nth 2 (car in-list))) + (setq sig (car in-list)) + ;; No current signal; form from existing details + (unless sv-name + (setq sv-name (verilog-sig-name sig) + sv-highbit nil + sv-busstring nil + sv-comment (verilog-sig-comment sig) + sv-memory (verilog-sig-memory sig) + sv-enum (verilog-sig-enum sig) + sv-signed (verilog-sig-signed sig) + combo "" + )) + ;; Extract bus details + (setq bus (verilog-sig-bits sig)) (cond ((and bus (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus) (setq highbit (string-to-int (match-string 1 bus)) ＠＠ -4721,32 +5076,40 ＠＠ (setq highbit (string-to-int (match-string 1 bus)) lowbit highbit)))) ;; Combine bits in bus - (if svhighbit - (setq svhighbit (max highbit svhighbit) - svlowbit (min lowbit svlowbit)) - (setq svhighbit highbit - svlowbit lowbit))) + (if sv-highbit + (setq sv-highbit (max highbit sv-highbit) + sv-lowbit (min lowbit sv-lowbit)) + (setq sv-highbit highbit + sv-lowbit lowbit))) (bus ;; String, probably something like `preproc:0 - (setq svbusstring bus))) - ;; Next + (setq sv-busstring bus))) + ;; Peek ahead to next signal (setq in-list (cdr in-list)) - (cond ((and in-list (equal (nth 0 (car in-list)) signal)) + (setq sig (car in-list)) + (cond ((and sig (equal sv-name (verilog-sig-name sig))) ;; Combine with this signal - (if (and svbusstring (not (equal svbusstring (nth 1 (car in-list))))) - (message (concat "Warning, can't merge into single bus " signal bus + (if (and sv-busstring (not (equal sv-busstring (verilog-sig-bits sig)))) + (message (concat "Warning, can't merge into single bus " + sv-name bus ", the AUTOs may be wrong"))) - (setq combo ", ...") - ) - (t ;; Doesn't match next signal, add to que, zero in prep for next + (if (verilog-sig-comment sig) (setq combo ", ...")) + (setq sv-memory (or sv-memory (verilog-sig-memory sig)) + sv-enum (or sv-enum (verilog-sig-enum sig)) + sv-signed (or sv-signed (verilog-sig-signed sig)))) + ;; Doesn't match next signal, add to que, zero in prep for next + ;; Note sig may also be nil for the last signal in the list + (t (setq out-list - (cons (list signal - (or svbusstring - (if svhighbit - (concat "[" (int-to-string svhighbit) ":" (int-to-string svlowbit) "]"))) - (concat comment combo)) + (cons (list sv-name + (or sv-busstring + (if sv-highbit + (concat "[" (int-to-string sv-highbit) ":" (int-to-string sv-lowbit) "]"))) + (concat sv-comment combo) + sv-memory sv-enum sv-signed) out-list) - svhighbit nil svbusstring nil combo "")))) + sv-name nil))) + ) ;; out-list)) ＠＠ -4764,7 +5127,7 ＠＠ (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary ;; Check for parameterized instantiations (when (looking-at ")") - (search-backward "(") + (verilog-backward-open-paren) (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)) (skip-chars-backward "a-zA-Z0-9'_$") (looking-at "[a-zA-Z0-9`_\$]+") ＠＠ -4816,7 +5179,7 ＠＠ (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max))) (functask 0) (paren 0) sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const - vec expect-signal keywd newsig rvalue enum) + vec expect-signal keywd newsig rvalue enum io signed) (save-excursion (verilog-beg-of-defun) (setq sigs-const (verilog-read-auto-constants (point) end-mod-point)) ＠＠ -4824,12 +5187,12 ＠＠ ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg))) (cond ((looking-at "//") - (if (looking-at "[^\n]+synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") + (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") (setq enum (match-string 1))) (search-forward "\n")) ((looking-at "/\\*") (forward-char 2) - (if (looking-at "[^*]+synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") + (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") (setq enum (match-string 1))) (or (search-forward "*/") (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) ＠＠ -4837,7 +5200,7 ＠＠ (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point)))) ((eq ?\; (following-char)) - (setq vec nil expect-signal nil newsig nil paren 0 rvalue nil) + (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil) (forward-char 1)) ((eq ?= (following-char)) (setq rvalue t newsig nil) ＠＠ -4872,24 +5235,27 ＠＠ (when (string-match "^\\\\" keywd) (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end (cond ((equal keywd "input") - (setq vec nil enum nil expect-signal 'sigs-in)) + (setq vec nil enum nil newsig nil signed nil io t expect-signal 'sigs-in)) ((equal keywd "output") - (setq vec nil enum nil expect-signal 'sigs-out)) + (setq vec nil enum nil newsig nil signed nil io t expect-signal 'sigs-out)) ((equal keywd "inout") - (setq vec nil enum nil expect-signal 'sigs-inout)) + (setq vec nil enum nil newsig nil signed nil io t expect-signal 'sigs-inout)) ((or (equal keywd "wire") (equal keywd "tri")) - (setq vec nil enum nil expect-signal 'sigs-wire)) + (unless io (setq vec nil enum nil signed nil expect-signal 'sigs-wire))) ((or (equal keywd "reg") (equal keywd "trireg")) - (setq vec nil enum nil expect-signal 'sigs-reg)) + (unless io (setq vec nil enum nil signed nil expect-signal 'sigs-reg))) ((equal keywd "assign") - (setq vec nil enum nil expect-signal 'sigs-assign)) + (setq vec nil enum nil signed nil expect-signal 'sigs-assign)) ((or (equal keywd "supply0") (equal keywd "supply1") (equal keywd "supply") - (equal keywd "parameter")) - (setq vec nil enum nil expect-signal 'sigs-const)) + (equal keywd "parameter") + (equal keywd "localparam")) + (unless io (setq vec nil enum nil signed nil expect-signal 'sigs-const))) + ((equal keywd "signed") + (setq signed "signed")) ((or (equal keywd "function") (equal keywd "task")) (setq functask (1+ functask))) ＠＠ -4898,9 +5264,10 ＠＠ (setq functask (1- functask))) ((and expect-signal (eq functask 0) + (not (member keywd verilog-keywords)) (not rvalue)) ;; Add new signal to expect-signal's variable - (setq newsig (list keywd vec nil nil enum)) + (setq newsig (list keywd vec nil nil enum signed)) (set expect-signal (cons newsig (symbol-value expect-signal)))))) (t ＠＠ -4916,40 +5283,70 ＠＠ (nreverse sigs-const) )))) -(defun verilog-read-sub-decls-line (comment) +(defvar sigs-in nil) ; Prevent compile warning +(defvar sigs-inout nil) ; Prevent compile warning +(defvar sigs-out nil) ; Prevent compile warning + +(defun verilog-read-sub-decls-line (submodi comment) "For read-sub-decl, read lines of port defs until none match anymore. -Return the list of signals found, using COMMENT for each signal." - (let (sigs) +Return the list of signals found, using submodi to look up each port." + (let (done port portdata sig vec) (save-excursion (forward-line 1) - (while (or - (if (looking-at "\\s-*\\.[^(]*(\\s-*\\(\\\\[^ \t\n]*\\)\\s-*)") - (let ((sig (concat (match-string 1) " ")) ;; escaped id's need trailing space - vec) - (or (equal sig "") - (setq sigs (cons (list sig vec comment) - sigs))))) - (if (looking-at "\\s-*\\.[^(]*(\\s-*\\([^[({)]*\\)\\s-*)") - (let ((sig (verilog-string-remove-spaces (match-string 1))) - vec) - (or (equal sig "") - (setq sigs (cons (list sig vec comment) - sigs))))) - (if (looking-at "\\s-*\\.[^(]*(\\s-*\\([^[({)]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)") - (let ((sig (verilog-string-remove-spaces (match-string 1))) - (vec (match-string 2))) - (or (equal sig "") - (setq sigs (cons (list sig vec comment) - sigs))))) - (looking-at "\\s-*\\.[^(]*(")) - (forward-line 1)) - sigs))) + (while (not done) + ;; Get port name + (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*") + (setq port (match-string 1)) + (goto-char (match-end 0))) + ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n]*\\)\\s-*(\\s-*") + (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space + (goto-char (match-end 0))) + ((looking-at "\\s-*\\.[^(]*(") + (setq port nil) ;; skip this line + (goto-char (match-end 0))) + (t + (setq port nil done t))) ;; Unknown, ignore rest of line + ;; Get signal name + (when port + (cond ((looking-at "\\(\\\\[^ \t\n]*\\)\\s-*)") + (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space + vec nil)) + ; We intentionally ignore (non-escaped) signals with .s in them + ; this prevents AUTOWIRE etc from noticing hierarchical sigs. + ((looking-at "\\([^[({).]*\\)\\s-*)") + (setq sig (verilog-string-remove-spaces (match-string 1)) + vec nil)) + ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)") + (setq sig (verilog-string-remove-spaces (match-string 1)) + vec (verilog-symbol-detick-denumber (match-string 2)))) + (t + (setq sig nil))) + ;; Process signals + (when sig + (setq port (verilog-symbol-detick-denumber port)) + (setq sig (verilog-symbol-detick-denumber sig)) + (unless (or (not sig) + (equal sig "")) ;; Ignore .foo(1'b1) assignments + (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi))) + (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil + (verilog-sig-signed portdata)) sigs-inout))) + ((setq portdata (assoc port (verilog-modi-get-outputs submodi))) + (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil + (verilog-sig-signed portdata)) sigs-out))) + ((setq portdata (assoc port (verilog-modi-get-inputs submodi))) + (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil + (verilog-sig-signed portdata)) sigs-in))) + ;; (t -- warning pin isn't defined.) ; Leave for lint tool + ) + ))) + ;; + (forward-line 1))))) (defun verilog-read-sub-decls () "Parse signals going to modules under this module. Return a array of [ outputs inouts inputs ] signals for modules that are instantiated in this module. For example if declare A A (.B(SIG)) and SIG -is a output, then it will be included in the list. +is a output, then SIG will be included in the list. This only works on instantiations created with /*AUTOINST*/ converted by \\[verilog-auto-instant]. Otherwise, it would have to read in the whole ＠＠ -4957,37 +5354,37 ＠＠ (save-excursion (let ((end-mod-point (verilog-get-end-of-defun t)) st-point end-inst-point - sigs-out sigs-inout sigs-in comment) + ;; below 3 modified by verilog-read-sub-decls-line + sigs-out sigs-inout sigs-in) (verilog-beg-of-defun) (while (search-forward "/*AUTOINST*/" end-mod-point t) (save-excursion (goto-char (match-beginning 0)) (unless (verilog-inside-comment-p) - (forward-line 1) ;; Attempt to snarf a comment - (setq comment (concat (verilog-read-inst-name) - " of " (verilog-read-inst-module) ".v")) + (let* ((submod (verilog-read-inst-module)) + (inst (verilog-read-inst-name)) + (comment (concat inst " of " submod ".v")) submodi) + (when (setq submodi (verilog-modi-lookup submod t)) ;; This could have used a list created by verilog-auto-instant - ;; However I want it to be runnable even if that function wasn't called before. + ;; However I want it to be runnable even on user's manually added signals (verilog-backward-open-paren) (setq end-inst-point (save-excursion (forward-sexp 1) (point)) st-point (point)) (while (re-search-forward "^\\s *// Outputs" end-inst-point t) - (setq sigs-out (append (verilog-read-sub-decls-line - (concat "From " comment)) sigs-out))) + (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out (goto-char st-point) (while (re-search-forward "\\s *// Inouts" end-inst-point t) - (setq sigs-inout (append (verilog-read-sub-decls-line - (concat "To/From " comment)) sigs-inout))) + (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout (goto-char st-point) (while (re-search-forward "\\s *// Inputs" end-inst-point t) - (setq sigs-in (append (verilog-read-sub-decls-line - (concat "To " comment)) sigs-in))) - ))) + (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in + ))))) ;; Combine duplicate bits - (vector (verilog-signals-combine-bus sigs-out) - (verilog-signals-combine-bus sigs-inout) - (verilog-signals-combine-bus sigs-in))))) + ;;(setq rr (vector sigs-out sigs-inout sigs-in)) + (vector (verilog-signals-combine-bus (nreverse sigs-out)) + (verilog-signals-combine-bus (nreverse sigs-inout)) + (verilog-signals-combine-bus (nreverse sigs-in)))))) (defun verilog-read-inst-pins () "Return a array of [ pins ] for the current instantiation at point. ＠＠ -5008,7 +5405,7 ＠＠ (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point pins pin) (verilog-backward-open-paren) - (while (re-search-forward "\\([a-zA-Z0-9`_$]+\\)" end-mod-point t) + (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t) (setq pin (match-string 1)) (unless (verilog-inside-comment-p) (setq pins (cons (list pin) pins)))) ＠＠ -5021,13 +5418,15 ＠＠ (let (sig-list tpl-end-pt) (goto-char beg) (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t) + (if (not (looking-at "\\s *(")) + (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text))) (search-forward "(" end-mod-point) (setq tpl-end-pt (save-excursion (backward-char 1) (forward-sexp 1) ;; Moves to paren that closes argdecl's (backward-char 1) (point))) - (while (re-search-forward "\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-*,*" tpl-end-pt t) + (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t) (setq sig-list (cons (list (match-string 1) nil nil) sig-list)))) sig-list))) ＠＠ -5046,7 +5445,7 ＠＠ ;; These are passed in a let, not global (if (not (boundp 'sigs-in)) (defvar sigs-in nil) (defvar sigs-out nil) - (defvar got-sig nil) (defvar got-rvalue nil))) + (defvar got-sig nil) (defvar got-rvalue nil) (defvar uses-delayed nil))) (defun verilog-read-always-signals-recurse (exit-keywd rvalue ignore-next) ＠＠ -5071,7 +5470,7 ＠＠ (point))) sig-last-tolk sig-tolk sig-tolk nil) - ;;(if dbg (setq dbg (concat dbg (format "\tPt %S %S\t%S %S\n" (point) keywd rvalue ignore-next)))) + ;;(if dbg (setq dbg (concat dbg (format "\tPt %S %S\t%S %S %S\n" (point) keywd rvalue ignore-next end-else-check)))) (cond ((equal keywd "\"") (or (re-search-forward "[^\\]\"" nil t) ＠＠ -5082,7 +5481,7 ＠＠ ;; no forward movement, want to see else in lower loop (setq end-else-check nil)) ;; End at top level loop - ((and end-else-check (looking-at "^[ \t\n]")) + ((and end-else-check (looking-at "[^ \t\n]")) ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd)))) (setq gotend t)) ;; Final statement? ＠＠ -5098,7 +5497,7 ＠＠ (setq end-else-check t)) (forward-char 1)) ((equal keywd "'") - (if (looking-at "'[odbhx][_xz?0-9a-fA-F \t]*") + (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*") (goto-char (match-end 0)) (forward-char 1))) ((equal keywd ":") ;; Case statement, begin/end label, x?y:z ＠＠ -5108,6 +5507,8 ＠＠ (setq ignore-next t rvalue nil))) (forward-char 1)) ((equal keywd "=") + (if (eq (char-before) ?< ) + (setq uses-delayed 1)) (setq ignore-next nil rvalue t) (forward-char 1)) ((equal keywd "?") ＠＠ -5128,8 +5529,9 ＠＠ ((equal keywd "begin") (skip-syntax-forward "w_") (verilog-read-always-signals-recurse "end" nil nil) + ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd)))) (setq ignore-next nil rvalue semi-rvalue) - (if (not exit-keywd) (setq gotend t))) ;; top level begin/end + (if (not exit-keywd) (setq end-else-check t))) ((or (equal keywd "case") (equal keywd "casex") (equal keywd "casez")) ＠＠ -5145,22 +5547,7 ＠＠ (string-match "^\\$" keywd)) ;; PLI task (setq ignore-next nil)) (t - (when (string-match "^`" keywd) - ;; This only will work if the define is a simple signal, not - ;; something like a[b]. Sorry, it should be substituted into the parser - (setq keywd - (verilog-string-replace-matches - "\[[^0-9: \t]+\]" "" nil nil - (or (verilog-symbol-detick keywd nil) - (if verilog-auto-sense-defines-constant - "0" - keywd)))) - (if (or (string-match "^[0-9 \t:]+$" keywd) - (string-match "^[---]*[0-9]+$" keywd) - (string-match "^[0-9 \t]+'[odbhx][_xz?0-9a-fA-F \t]*$" keywd) - ) - (setq keywd nil)) - ) + (setq keywd (verilog-symbol-detick-denumber keywd)) (if got-sig (if got-rvalue (setq sigs-in (cons got-sig sigs-in)) (setq sigs-out (cons got-sig sigs-out)))) ＠＠ -5185,7 +5572,8 ＠＠ (save-excursion (let* (;;(dbg "") sigs-in sigs-out - got-sig got-rvalue) ;; Found signal/rvalue; push if not function + got-sig got-rvalue + uses-delayed) ;; Found signal/rvalue; push if not function (search-forward ")") (verilog-read-always-signals-recurse nil nil nil) ;; Return what was found ＠＠ -5193,7 +5581,7 ＠＠ (setq sigs-in (cons got-sig sigs-in)) (setq sigs-out (cons got-sig sigs-out)))) ;;(if dbg (message dbg)) - (list sigs-out nil sigs-in)))) + (list sigs-out nil sigs-in uses-delayed)))) (defun verilog-read-instants () "Parse module at point and return list of ( ( file instance ) ... )." ＠＠ -5228,13 +5616,18 ＠＠ ( (signal_name connection_name)... )" (save-excursion ;; Find beginning - (let (tpl-sig-list tpl-wild-list tpl-end-pt rep) + (let (tpl-sig-list tpl-wild-list tpl-end-pt rep (lineno 0) (templateno 0)) (cond ((or (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t) (progn (goto-char (point-min)) (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t))) (search-forward "(") + (when verilog-auto-inst-template-numbers + (save-excursion + (goto-char (point-min)) + (while (search-forward "AUTO_TEMPLATE" nil t) + (setq templateno (1+ templateno))))) (setq tpl-end-pt (save-excursion (backward-char 1) (forward-sexp 1) ;; Moves to paren that closes argdecl's ＠＠ -5244,41 +5637,73 ＠＠ (while (< (point) tpl-end-pt) (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)") (setq tpl-sig-list (cons (list - (match-string 1) - (match-string 2)) - tpl-sig-list))) + (match-string-no-properties 1) + (match-string-no-properties 2) + templateno lineno) + tpl-sig-list)) + (goto-char (match-end 0))) ;; Regexp form?? ((looking-at ;; Regexp bug in xemacs disallows ][ inside [], and wants + last - &quot;\\s-*\\.\\(\\([a-zA-Z0-9`_$+(a)^.*?---]+\\|[][]\\|\\\\[()]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)&quot;) - (setq rep (match-string 3)) + &quot;\\s-*\\.\\(\\([a-zA-Z0-9`_$+(a)^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)&quot;) + (setq rep (match-string-no-properties 3)) + (goto-char (match-end 0)) (setq tpl-wild-list (cons (list (concat "^" (verilog-string-replace-matches "＠" "\\\\([0-9]+\\\\)" nil nil (match-string 1)) "$") - rep) - tpl-wild-list)))) - (forward-line 1)) + rep + templateno lineno) + tpl-wild-list))) + ((looking-at "[ \t\f]+") + (goto-char (match-end 0))) + ((looking-at "\n") + (setq lineno (1+ lineno)) + (goto-char (match-end 0))) + ((looking-at "//") + (search-forward "\n")) + ((looking-at "/\\*") + (forward-char 2) + (or (search-forward "*/") + (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) + (t + (error "%s: AUTO_TEMPLATE parsing error: %s" + (verilog-point-text) + (progn (looking-at ".*$") (match-string 0)))) + )) ;; (list tpl-sig-list tpl-wild-list) ))))) ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry")) -(defun verilog-set-define (defname defvalue &optional buffer) +(defun verilog-set-define (defname defvalue &optional buffer enumname) "In BUFFER, set the definition DEFNAME to the DEFVALUE." (save-excursion (set-buffer (or buffer (current-buffer))) (let ((mac (intern (concat "vh-" defname)))) + ;;(message "Define %s=%s" defname defvalue) (sleep-for 1) + (set (make-variable-buffer-local mac) defvalue)) + (if enumname + (let ((enumvar (intern (concat "venum-" enumname)))) ;;(message "Define %s=%s" defname defvalue) (sleep-for 1) - (set (make-variable-buffer-local mac) defvalue)))) + (make-variable-buffer-local enumvar) + (add-to-list enumvar defname))) + )) (defun verilog-read-defines (&optional filename recurse) - "Read `defines for the current file, or from the optional FILENAME. + "Read `defines and parameters for the current file, or optional FILENAME. If the filename is provided, `verilog-library-directories' and -`verilog-library-extensions' will be used to resolve it. -If optional RECURSE is non-nil, recurse through `includes. +`verilog-library-extensions' will be used to resolve it. If optional +RECURSE is non-nil, recurse through `includes. + +Parameters must be simple assignments to constants, or have their own +\"parameter\" label rather then a list of parameters. Thus: + + parameter X = 5, Y = 10; // Ok + parameter X = {1'b1, 2'h2}; // Ok + parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines Defines must be simple text substitutions, one on a line, starting at the beginning of the line. Any ifdefs or multiline comments around the ＠＠ -5303,7 +5728,13 ＠＠ // End: Note these are only read when the file is first visited, you must use -\\[find-alternate-file] RET to have these take effect after editing them!" +\\[find-alternate-file] RET to have these take effect after editing them! + +If you want to disable the \"Process `eval' or hook local variables\" +warning message, you need to add to your .emacs file: + +(setq enable-local-eval t) +" (let ((origbuf (current-buffer))) (save-excursion (when filename ＠＠ -5315,19 +5746,36 ＠＠ (when recurse (goto-char (point-min)) (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n]+\\)" nil t) - (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1)))) - (verilog-read-defines inc recurse)))) + (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1)))) + (unless (verilog-inside-comment-p) + (verilog-read-defines inc recurse))))) ;; Read `defines + ;; note we don't use verilog-re... it's faster this way, and that + ;; function has problems when comments are at the end of the define (goto-char (point-min)) - (while (verilog-re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t) - (let ((defname (match-string 1)) - (defvalue (match-string 2))) + (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t) + (let ((defname (match-string-no-properties 1)) + (defvalue (match-string-no-properties 2))) (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue)) (verilog-set-define defname defvalue origbuf))) ;; Hack: Read parameters (goto-char (point-min)) - (while (verilog-re-search-forward "^\\s-*parameter\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+=\\s-+\\([^;]*\\)" nil t) - (verilog-set-define (match-string 1) (match-string 2) origbuf)) + (while (re-search-forward + "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t) + (let ((var (match-string-no-properties 4)) + (val (match-string-no-properties 5)) + enumname) + ;; The primary way of getting defines is verilog-read-decls + ;; However, that isn't called yet for included files, so we'll add another scheme + (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") + (setq enumname (match-string-no-properties 1))) + (if var + (verilog-set-define var val origbuf enumname)) + (forward-comment 999) + (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*") + (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname) + (goto-char (match-end 0)) + (forward-comment 999)))) ))) (defun verilog-read-includes () ＠＠ -5373,7 +5821,7 ＠＠ (progn;save-excursion (goto-char (or start (point-min))) (setq end (or end (point-max))) - (while (re-search-forward "[\"/a-zA-Z_]" end t) + (while (re-search-forward "[\"/a-zA-Z_.%`]" end t) (forward-char -1) (cond ((looking-at "//") ＠＠ -5382,7 +5830,7 ＠＠ (search-forward "*/")) ((eq ?\" (following-char)) (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first - ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\)") + ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)") (goto-char (match-end 0)) (setq keywd (match-string-no-properties 1)) (or (member keywd verilog-keywords) ＠＠ -5419,18 +5867,47 ＠＠ (setq pt (point)))) pt)))) +(defun verilog-is-number (symbol) + "Return true if SYMBOL is number-like." + (or (string-match "^[0-9 \t:]+$" symbol) + (string-match "^[---]*[0-9]+$" symbol) + (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol) + )) + (defun verilog-symbol-detick (symbol wing-it) "Return a expanded SYMBOL name without any defines. If the variable vh-{symbol} is defined, return that value. If undefined, and WING-IT, return just SYMBOL without the tick, else nil." (while (and symbol (string-match "^`" symbol)) (setq symbol (substring symbol 1)) + (setq symbol (if (boundp (intern (concat "vh-" symbol))) - (setq symbol (eval (intern (concat "vh-" symbol)))) - (if (not wing-it) (setq symbol nil)))) + ;; Emacs has a bug where boundp on a buffer-local variable in only one + ;; buffer returns t in another. This can confuse, so check for nil. + (let ((val (eval (intern (concat "vh-" symbol))))) + (if (eq val nil) + (if wing-it symbol nil) + val)) + (if wing-it symbol nil)))) symbol) ;;(verilog-symbol-detick "`mod" nil) +(defun verilog-symbol-detick-denumber (symbol) + "Return symbol with defines converted and any numbers dropped to nil." + (when (string-match "^`" symbol) + ;; This only will work if the define is a simple signal, not + ;; something like a[b]. Sorry, it should be substituted into the parser + (setq symbol + (verilog-string-replace-matches + "\[[^0-9: \t]+\]" "" nil nil + (or (verilog-symbol-detick symbol nil) + (if verilog-auto-sense-defines-constant + "0" + symbol))))) + (if (verilog-is-number symbol) + nil + symbol)) + (defun verilog-expand-dirnames (&optional dirnames) "Return a list of existing directories given a list of wildcarded dirnames or just the existing dirnames themselves if there are no wildcards." ＠＠ -5440,7 +5917,7 ＠＠ (let ((dirlist nil) pattern dirfile dirfiles dirname root filename rest) (while dirnames - (setq dirname (car dirnames) + (setq dirname (substitute-in-file-name (car dirnames)) dirnames (cdr dirnames)) (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *? ＠＠ -5476,7 +5953,7 ＠＠ (defun verilog-library-filenames (filename current) "Return a search path to find the given FILENAME name. Uses the CURRENT filename, `verilog-library-directories' and -`verilog-library-extensions` variables to build the path." +`verilog-library-extensions' variables to build the path." (let ((ckdir (verilog-expand-dirnames verilog-library-directories)) fn outlist) (while ckdir ＠＠ -5579,16 +6056,27 ＠＠ (defsubst verilog-modi-name (modi) (aref modi 0)) +(defsubst verilog-modi-file-or-buffer (modi) + (aref modi 1)) +(defsubst verilog-modi-point (modi) + (aref modi 2)) + +(defun verilog-modi-filename (modi) + "Filename of modi, or name of buffer if its never been saved" + (if (bufferp (verilog-modi-file-or-buffer modi)) + (or (buffer-file-name (verilog-modi-file-or-buffer modi)) + (buffer-name (verilog-modi-file-or-buffer modi))) + (verilog-modi-file-or-buffer modi))) (defun verilog-modi-goto (modi) "Move point/buffer to specified MODI." (or modi (error "Passed unfound modi to goto, check earlier")) - (set-buffer (if (bufferp (aref modi 1)) - (aref modi 1) - (find-file-noselect (aref modi 1)))) + (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi)) + (verilog-modi-file-or-buffer modi) + (find-file-noselect (verilog-modi-file-or-buffer modi)))) (or (equal major-mode `verilog-mode) ;; Put into verilog mode to get syntax (verilog-mode)) - (goto-char (aref modi 2))) + (goto-char (verilog-modi-point modi))) (defun verilog-goto-defun-file (module) "Move point to the file at which a given MODULE is defined." ＠＠ -5664,52 +6152,7 ＠＠ (verilog-modi-cache-preserve-buffer (current-buffer))) (progn ,＠body))) -(defsubst verilog-modi-get-decls (modi) - (verilog-modi-cache-results modi 'verilog-read-decls)) - -(defsubst verilog-modi-get-sub-decls (modi) - (verilog-modi-cache-results modi 'verilog-read-sub-decls)) - -;; Signal reading for given module -;; Note these all take modi's - as returned from the verilog-modi-current function -(defsubst verilog-modi-get-outputs (modi) - (aref (verilog-modi-get-decls modi) 0)) -(defsubst verilog-modi-get-inouts (modi) - (aref (verilog-modi-get-decls modi) 1)) -(defsubst verilog-modi-get-inputs (modi) - (aref (verilog-modi-get-decls modi) 2)) -(defsubst verilog-modi-get-wires (modi) - (aref (verilog-modi-get-decls modi) 3)) -(defsubst verilog-modi-get-regs (modi) - (aref (verilog-modi-get-decls modi) 4)) -(defsubst verilog-modi-get-assigns (modi) - (aref (verilog-modi-get-decls modi) 5)) -(defsubst verilog-modi-get-consts (modi) - (aref (verilog-modi-get-decls modi) 6)) -(defsubst verilog-modi-get-sub-outputs (modi) - (aref (verilog-modi-get-sub-decls modi) 0)) -(defsubst verilog-modi-get-sub-inouts (modi) - (aref (verilog-modi-get-sub-decls modi) 1)) -(defsubst verilog-modi-get-sub-inputs (modi) - (aref (verilog-modi-get-sub-decls modi) 2)) -;; Elements of a signal list -(defsubst verilog-sig-name (sig) - (car sig)) -(defsubst verilog-sig-bits (sig) - (nth 1 sig)) -(defsubst verilog-sig-comment (sig) - (nth 2 sig)) -(defsubst verilog-sig-memory (sig) - (nth 3 sig)) -(defsubst verilog-sig-enum (sig) - (nth 4 sig)) - -(defsubst verilog-alw-get-inputs (sigs) - (nth 2 sigs)) -(defsubst verilog-alw-get-outputs (sigs) - (nth 0 sigs)) - (defun verilog-signals-matching-enum (in-list enum) "Return all signals in IN-LIST matching the given ENUM." (let (out-list) ＠＠ -5717,6 +6160,12 ＠＠ (if (equal (verilog-sig-enum (car in-list)) enum) (setq out-list (cons (car in-list) out-list))) (setq in-list (cdr in-list))) + ;; New scheme + (let* ((enumvar (intern (concat "venum-" enum))) + (enumlist (and (boundp enumvar) (eval enumvar)))) + (while enumlist + (add-to-list 'out-list (list (car enumlist))) + (setq enumlist (cdr enumlist)))) (nreverse out-list))) ;; Combined ＠＠ -5784,11 +6233,14 ＠＠ (let ((sig (car sigs))) (indent-to indent-pt) (insert type) + (when (verilog-sig-signed sig) + (insert " " (verilog-sig-signed sig))) (when (verilog-sig-bits sig) (insert " " (verilog-sig-bits sig))) (indent-to (max 24 (+ indent-pt 16))) (insert (concat (verilog-sig-name sig) ";")) - (if (not (verilog-sig-comment sig)) + (if (or (not (verilog-sig-comment sig)) + (equal "" (verilog-sig-comment sig))) (insert "\n") (indent-to (max 48 (+ indent-pt 40))) (insert (concat "// " (verilog-sig-comment sig) "\n"))) ＠＠ -5827,18 +6279,21 ＠＠ "Return an expression calculating the length of a range [x:y]." (interactive) ;; strip off the [] - (string-match "\\[\\([^]]*\\)\\]" range-exp) - (setq range-exp (match-string 1 range-exp)) - (setq range-exp (verilog-symbol-detick range-exp t)) - (cond ((string-match "\\([^:]*\\):\\([^]]*\\)" range-exp) ;; a range z:y - (let ((range-exp-1 (match-string 1 range-exp)) - (range-exp-2 (match-string 2 range-exp))) - (concat "+1+abs(" range-exp-1 "-" range-exp-2 ")"))) - ((string-match "\\([0-9]+\\)" range-exp) ;; a range number - (let ((range-exp-1 (match-string 1 range-exp))) - (concat "+1"))) - ((concat "+" range-exp)) - )) + (cond ((not range-exp) + "1") + (t + (if (string-match "^\\[\\(.*\\)\\]$" range-exp) + (setq range-exp (match-string 1 range-exp))) + (cond ((not range-exp) + "1") + ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$" range-exp) + (int-to-string (1+ (abs (- (string-to-int (match-string 1 range-exp)) + (string-to-int (match-string 2 range-exp))))))) + ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp) + (concat "(1+(" (match-string 1 range-exp) + ")-(" (match-string 2 range-exp) "))")) + (t nil))))) +;;(verilog-make-width-expression "`A:`B")  ;; ＠＠ -5888,7 +6343,7 ＠＠ (if (buffer-file-name) (find-file-noselect (buffer-file-name))) ;; To check we have latest version ;; Remove those that have multi-line insertions - (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|RESET\\)\\*/" + (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\)\\*/" 'verilog-delete-autos-lined) ;; Remove those that have multi-line insertions with parameters (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/" ＠＠ -5899,10 +6354,9 ＠＠ ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed (goto-char (point-min)) - (while (re-search-forward "\\s-*// Templated\\s-*$" nil t) + (while (re-search-forward "\\s-*// Templated[ \tLT0-9]*$" nil t) (replace-match "")))) - ;; ;; Auto save ;; ＠＠ -5929,6 +6383,23 ＠＠ )) nil) ;; Always return nil -- we don't write the file ourselves  +(defun verilog-auto-read-locals () + "Return file local variable segment at bottom of file." + (save-excursion + (goto-char (point-max)) + (if (re-search-backward "Local Variables:" nil t) + (buffer-substring-no-properties (point) (point-max)) + ""))) + +(defun verilog-auto-reeval-locals (&optional just-cache) + "Read file local variable segment at bottom of file if it's changed since last read." + (make-variable-buffer-local 'verilog-auto-last-file-locals) + (let ((curlocal (verilog-auto-read-locals))) + (when (not (equal verilog-auto-last-file-locals curlocal)) + (unless just-cache (hack-local-variables)) + (setq verilog-auto-last-file-locals curlocal) + t))) + ;; ;; Auto creation ;; ＠＠ -6016,7 +6487,10 ＠＠ nil) (defvar vector-skip-list nil) ; Prevent compile warning - +(defvar vl-cell-type nil "See verilog-auto-inst") ; Prevent compile warning +(defvar vl-cell-name nil "See verilog-auto-inst") ; Prevent compile warning +(defvar vl-width 0) +(defvar vl-name 0) (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num) "Print out a instantiation connection for this PORT-ST. Insert to INDENT-PT, use template TPL-LIST. ＠＠ -6027,6 +6501,7 ＠＠ (verilog-auto-inst-port-map port-st))) ;; vl-* are documented for user use (vl-name (verilog-sig-name port-st)) + (vl-width (verilog-sig-width port-st)) (vl-bits (if (or verilog-auto-inst-vector (not (assoc port vector-skip-list)) (not (equal (verilog-sig-bits port-st) ＠＠ -6042,7 +6517,7 ＠＠ (let ((wildcards (nth 1 tpl-list))) (while wildcards (when (string-match (nth 0 (car wildcards)) port) - (setq tpl-ass t ; so allow ＠ parsing + (setq tpl-ass (car wildcards) ; so allow ＠ parsing tpl-net (replace-match (nth 1 (car wildcards)) t nil port))) (setq wildcards (cdr wildcards)))))) ＠＠ -6076,7 +6551,10 ＠＠ (insert "(" tpl-net "),") (when tpl-ass (indent-to 64) - (insert " // Templated")) + (insert " // Templated") + (when verilog-auto-inst-template-numbers + (insert " T" (int-to-string (nth 2 tpl-ass)) + " L" (int-to-string (nth 3 tpl-ass))))) (insert "\n"))) ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a＠\"(% (+ ＠ 1) 4)\"a")) "3") ;;(x "incom[＠\"(+ (* 8 ＠) 7)\":＠\"(* 8 ＠)\"]") ＠＠ -6214,6 +6692,11 ＠＠ alone to mean active low. Note the use of [] to keep the bus subscript: .\\(.*\\)_l (\\1_[]),  + If you have a complicated template, set `verilog-auto-inst-template-numbers' + to see which regexps are matching. Don't leave that mode set after + debugging is completed though, it will result in lots of extra differences + and merge conflicts. + Lisp templates: First any regular expression template is expanded. ＠＠ -6224,8 +6707,12 ＠＠ brackets. Quote all double-quotes inside the expression with a leading backslash (\\\"). There are special variables defined that are useful in these Lisp functions: - vl-name name portion of the input/output port - vl-bits bus bits portion of the input/output port ('[2:0]') + vl-name Name portion of the input/output port + vl-bits Bus bits portion of the input/output port ('[2:0]') + vl-width Width of the input/output port ('3' for [2:0]) + May be a (...) expression if bits isn't a constant. + vl-cell-type Module name/type of the cell ('psm_mas') + vl-cell-name Instance name of the cell ('ms2m') Normal Lisp variables may be used in expressions. See `verilog-read-defines' which can set vh-{definename} variables for use ＠＠ -6235,7 +6722,7 ＠＠ will evaluate any Lisp expression inside the parenthesis between the beginning of the buffer and the point of the AUTOINST. This allows - variables to be changed between each instantiation. + functions to be defined or variables to be changed between instantiations. After the evaluation is completed, ＠ substitution and [] substitution occur." ＠＠ -6251,6 +6738,8 ＠＠ ;; Find module name that is instantiated (setq submod (verilog-read-inst-module) inst (verilog-read-inst-name) + vl-cell-type submod + vl-cell-name inst skip-pins (aref (verilog-read-inst-pins) 0)) ;; Parse any AUTO_LISP() before here ＠＠ -6484,7 +6973,7 ＠＠ module ex_output (ov,i) input i; - /*AUTOWIRE*/ + /*AUTOOUTPUT*/ inst inst (/*AUTOINST*/); endmodule ＠＠ -6556,10 +7045,11 ＠＠ ;;Point must be at insertion point (let* ((indent-pt (current-indentation)) (modi (verilog-modi-current)) - (sig-list (verilog-signals-not-in + (sig-list (verilog-signals-combine-bus + (verilog-signals-not-in (verilog-modi-get-signals modi) (verilog-modi-get-ports modi) - ))) + )))) (forward-line 1) (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n") (verilog-insert-definition sig-list "output" indent-pt) ＠＠ -6621,6 +7111,58 ＠＠ (verilog-insert-indent "// End of automatics\n") ))) +(defun verilog-auto-inout () + "Expand AUTOINOUT statements, as part of \\[verilog-auto]. +Make inout statements for any inout signal in an /*AUTOINST*/ that +isn't declared elsewhere inside the module. + +Limitations: + This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decl). + + If any concatenation, or bit-subscripts are missing in the AUTOINSTant's + instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). + +A simple example (see `verilog-auto-inst' for what else is going on here): + + module ex_inout (ov,i) + input i; + /*AUTOINOUT*/ + inst inst (/*AUTOINST*/); + endmodule + +Typing \\[verilog-auto] will make this into: + + module ex_inout (ov,i) + input i; + /*AUTOINOUT*/ + // Beginning of automatic inouts (from unused autoinst inouts) + inout [31:0] ov; // From inst of inst.v + // End of automatics + inst inst (/*AUTOINST*/ + // Inouts + .ov (ov[31:0]), + // Inputs + .i (i)); + endmodule" + (save-excursion + ;; Point must be at insertion point. + (let* ((indent-pt (current-indentation)) + (modi (verilog-modi-current)) + (sig-list (verilog-signals-not-in + (verilog-modi-get-sub-inouts modi) + (append (verilog-modi-get-outputs modi) + (verilog-modi-get-inouts modi) + (verilog-modi-get-inputs modi) + (verilog-modi-get-sub-inputs modi) + (verilog-modi-get-sub-outputs modi) + )))) + (forward-line 1) + (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n") + (verilog-insert-definition sig-list "inout" indent-pt) + (verilog-modi-cache-add-inouts modi sig-list) + (verilog-insert-indent "// End of automatics\n") + ))) + (defun verilog-auto-inout-module () "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto]. Take input/output/inout statements from the specified module and insert ＠＠ -6733,8 +7275,11 ＠＠ end" (save-excursion ;; Find beginning - (let* ((indent-pt (save-excursion - (or (and (search-backward "(" nil t) (1+ (current-column))) + (let* ((start-pt (save-excursion + (verilog-re-search-backward "(" nil t) + (point))) + (indent-pt (save-excursion + (or (and (goto-char start-pt) (1+ (current-column))) (current-indentation)))) (modi (verilog-modi-current)) (sig-memories (verilog-signals-memory (verilog-modi-get-regs modi))) ＠＠ -6742,21 +7287,28 ＠＠ ;; Read signals in always, eliminate outputs from sense list (setq presense-sigs (verilog-signals-from-signame (save-excursion - (verilog-read-signals (save-excursion - (verilog-re-search-backward "(" nil t) - (point)) - (point))))) + (verilog-read-signals start-pt (point))))) (setq sigss (verilog-read-always-signals)) - (setq sig-list (verilog-signals-not-in (verilog-alw-get-inputs sigss) + (setq sig-list (verilog-signals-not-params + (verilog-signals-not-in (verilog-alw-get-inputs sigss) (append (and (not verilog-auto-sense-include-inputs) (verilog-alw-get-outputs sigss)) (verilog-modi-get-consts modi) presense-sigs) - )) + ))) (when sig-memories (let ((tlen (length sig-list))) (setq sig-list (verilog-signals-not-in sig-list sig-memories)) (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ ")))) + (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/" + (save-excursion (goto-char (point)) + (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t) + (verilog-re-search-backward "\\s-" start-pt t) + (while (looking-at "\\s-`endif") + (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t) + (verilog-re-search-backward "\\s-" start-pt t)) + (not (looking-at "\\s-or\\b")))) + (setq not-first t)) (setq sig-list (sort sig-list `verilog-signals-sort-compare)) (while sig-list (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or ＠＠ -6776,13 +7328,12 ＠＠ Limitations: AUTORESET will not clear memories. + AUTORESET uses <= if there are any <= in the block, else it uses =. -OOps! - If AUTORESET makes a mistake, please report it. (First make sure - you have begin/end after your always!) As a workaround, if a signal - should be in the sensitivity list wasn't, placing it before the - /*AUTORESET*/ comment will prevent it from being deleted when the - autos are updated (or added if it occurs there already). +/*AUTORESET*/ presumes that any signals mentioned between the previous +begin/case/if statement and the AUTORESET comment are being reset manually +and should not be automatically reset. This includes ommitting any signals +used on the right hand side of assignments. A simple example: ＠＠ -6820,7 +7371,9 ＠＠ (save-excursion ;; Find beginning (let* ((indent-pt (current-indentation)) - sigss sig-list prereset-sigs) + (modi (verilog-modi-current)) + (all-list (verilog-modi-get-signals modi)) + sigss sig-list prereset-sigs assignment-str) ;; Read signals in always, eliminate outputs from reset list (setq prereset-sigs (verilog-signals-from-signame (save-excursion ＠＠ -6832,6 +7385,9 ＠＠ (save-excursion (verilog-re-search-backward "＠" nil t) (setq sigss (verilog-read-always-signals))) + (setq assignment-str (if (verilog-alw-get-uses-delayed sigss) + (concat " <= " verilog-assignment-delay) + " = ")) (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss) prereset-sigs)) (setq sig-list (sort sig-list `verilog-signals-sort-compare)) ＠＠ -6840,10 +7396,18 ＠＠ (insert "// Beginning of autoreset for uninitialized flops\n"); (indent-to indent-pt) (while sig-list + (let* ((defn-sig (if verilog-auto-reset-widths + (assoc (verilog-sig-name (car sig-list)) all-list))) + (width (if defn-sig (verilog-sig-width defn-sig)))) (insert (verilog-sig-name (car sig-list))) - (insert " <= 0;\n") + (cond ((not width) + (insert assignment-str "0;\n")) + ((string-match "^[0-9]+$" width) + (insert assignment-str (verilog-sig-width defn-sig) "'h0;\n" )) + (t + (insert assignment-str "{" (verilog-sig-width defn-sig) "{1'b0}};\n" ))) (indent-to indent-pt) - (setq sig-list (cdr sig-list))) + (setq sig-list (cdr sig-list)))) (insert "// End of automatics") ))) ＠＠ -6905,7 +7469,7 ＠＠ // Beginning of automatic ASCII enum decoding reg [39:0] _stateascii_r; // Decode of state_r always ＠(state_r) begin - casex ({state_r}) // synopsys full_case parallel_case + case ({state_r}) SM_IDLE: _stateascii_r = \"idle \"; SM_SEND: _stateascii_r = \"send \"; SM_WAIT1: _stateascii_r = \"wait1\"; ＠＠ -6959,7 +7523,7 ＠＠ (verilog-insert-indent "always ＠(" undecode-name ") begin\n") (setq indent-pt (+ indent-pt verilog-indent-level)) (indent-to indent-pt) - (insert "casex ({" undecode-name "}) // synopsys full_case parallel_case\n") + (insert "case ({" undecode-name "})\n") (setq indent-pt (+ indent-pt verilog-case-indent)) ;; (let ((tmp-sigs enum-sigs) ＠＠ -6981,6 +7545,26 ＠＠ "// End of automatics\n") ))) +(defun verilog-auto-templated-rel () + "Replace Templated relative line numbers with absolute line numbers. +Internal use only. This hacks around the line numbers in AUTOINST Templates +being different from the final output's line numbering." + (let ((templateno 0) (template-line (list 0))) + ;; Find line number each template is on + (goto-char (point-min)) + (while (search-forward "AUTO_TEMPLATE" nil t) + (setq templateno (1+ templateno)) + (setq template-line (cons (count-lines (point-min) (point)) template-line))) + (setq template-line (nreverse template-line)) + ;; Replate T# L# with absolute line number + (goto-char (point-min)) + (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t) + (replace-match (concat " Templated " + (int-to-string (+ (nth (string-to-int (match-string 1)) + template-line) + (string-to-int (match-string 2))))) + t t)))) +  ;; ;; Auto top level ＠＠ -7012,6 +7596,7 ＠＠ `verilog-auto-arg' for AUTOARG module instantiations `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere + `verilog-auto-inout' for AUTOINOUT making hierarchy inouts `verilog-auto-input' for AUTOINPUT making hierarchy inputs `verilog-auto-inst' for AUTOINST argument declarations `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs ＠＠ -7043,7 +7628,9 ＠＠ t))) (save-excursion (run-hooks 'verilog-before-auto-hook) - ;; This may seem obvious to do, but on large includes it can be way too slow + ;; Try to save the user from needing to revert-file to reread file local-variables + (verilog-auto-reeval-locals) + ;; These two may seem obvious to do always, but on large includes it can be way too slow (when verilog-auto-read-includes (verilog-read-includes) (verilog-read-defines)) ＠＠ -7059,23 +7646,23 ＠＠ (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset) ;; Must be done before autoin/out as creates a reg (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum) - ) ;; - ;; Inputs/outputs are mutually independent - (verilog-preserve-cache ;; first in/outs from other files (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module) ;; next in/outs which need previous sucked inputs first (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output) (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input) - ;; outputevery needs autooutputs done first - (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every) + (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout) ;; Wires/regs must be after inputs/outputs (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire) (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg) (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input) + ;; outputevery needs autooutputs done first + (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every) ;; Must be after all inputs outputs are generated (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg) + ;; Fix line numbers (comments only) + (verilog-auto-templated-rel) ) ;; (run-hooks 'verilog-auto-hook) ＠＠ -7474,6 +8061,133 ＠＠  ;; +;; Include file loading with mouse/return event +;; +;; idea & first impl.: M. Rouat (eldo-mode.el) +;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el) + +(if verilog-running-on-xemacs + (require 'overlay) + (require 'lucid)) ;; what else can we do ?? + +(defconst verilog-include-file-regexp + "^`include\\s-+\"\\([^\n\"]*\\)\"" + "Regexp that matches the include file") + +(defvar verilog-mode-mouse-map nil + "Map containing mouse bindings for verilog-mode.") + +(if verilog-mode-mouse-map + () + (let ((map (make-sparse-keymap))) ; as described in info pages, make a map + (set-keymap-parent map verilog-mode-map) + ;; mouse button bindings + (define-key map "\r" 'verilog-load-file-at-point) + (if verilog-running-on-xemacs + (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ? + (define-key map [mouse-2] 'verilog-load-file-at-mouse)) + (if verilog-running-on-xemacs + (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ? + (define-key map [S-mouse-2] 'mouse-yank-at-click)) + (setq verilog-mode-mouse-map map))) ;; copy complete map now + +;; create set-extent-keymap procedure when it does not exist +(eval-and-compile + (unless (fboundp 'set-extent-keymap) + (defun set-extent-keymap (extent keymap) + "fallback version of set-extent-keymap (for emacs 2[01])" + (set-extent-property extent 'local-map keymap)))) + +(defun verilog-colorize-include-files (beg end old-len) + "This function colorises included files when the mouse passes over them. +Clicking on the middle-mouse button loads them in a buffer (as in dired)." + (save-excursion + (save-match-data + (let (end-point) + (goto-char end) + (setq end-point (verilog-get-end-of-line)) + (goto-char beg) + (beginning-of-line) ; scan entire line ! + ;; delete overlays existing on this line + (let ((overlays (overlays-in (point) end-point))) + (while overlays + (if (and + (overlay-get (car overlays) 'detachable) + (overlay-get (car overlays) 'verilog-include-file)) + (delete-overlay (car overlays))) + (setq overlays (cdr overlays)))) ; let + ;; make new ones, could reuse deleted one ? + (while (search-forward-regexp verilog-include-file-regexp end-point t) + (let (extent) + (goto-char (match-beginning 1)) + (or (extent-at (point) (buffer-name) 'mouse-face) ;; not yet extended + (progn + (setq extent (make-extent (match-beginning 1) (match-end 1))) + (set-extent-property extent 'start-closed 't) + (set-extent-property extent 'end-closed 't) + (set-extent-property extent 'detachable 't) + (set-extent-property extent 'verilog-include-file 't) + (set-extent-property extent 'mouse-face 'highlight) + (set-extent-keymap extent verilog-mode-mouse-map))))))))) + + +(defun verilog-colorize-include-files-buffer () + (interactive) + ;; delete overlays + (let ((overlays (overlays-in (point-min) (point-max)))) + (while overlays + (if (and + (overlay-get (car overlays) 'detachable) + (overlay-get (car overlays) 'verilog-include-file)) + (delete-overlay (car overlays))) + (setq overlays (cdr overlays)))) ; let + ;; remake overlays + (verilog-colorize-include-files (point-min) (point-max) nil)) + +;; ffap-at-mouse isn't useful for verilog mode. It uses library paths. +;; so define this function to do more or less the same as ffap-at-mouse +;; but first resolve filename... +(defun verilog-load-file-at-mouse (event) + "loads file under button 2 click. Files are checked based on +`verilog-library-directories'." + (interactive "＠e") + (save-excursion ;; implement a verilog specific ffap-at-mouse + (mouse-set-point event) + (beginning-of-line) + (if (looking-at verilog-include-file-regexp) + (if (and (car (verilog-library-filenames + (match-string 1) (buffer-file-name))) + (file-readable-p (car (verilog-library-filenames + (match-string 1) (buffer-file-name))))) + (find-file (car (verilog-library-filenames + (match-string 1) (buffer-file-name)))) + (progn + (message + "File '%s' isn't readable, use shift-mouse2 to paste in this field" + (match-string 1)))) + ))) + +;; ffap isn't useable for verilog mode. It uses library paths. +;; so define this function to do more or less the same as ffap +;; but first resolve filename... +(defun verilog-load-file-at-point () + "loads file under point. Files are checked based on +`verilog-library-directories'." + (interactive) + (save-excursion ;; implement a verilog specific ffap + (beginning-of-line) + (if (looking-at verilog-include-file-regexp) + (if (and + (car (verilog-library-filenames + (match-string 1) (buffer-file-name))) + (file-readable-p (car (verilog-library-filenames + (match-string 1) (buffer-file-name))))) + (find-file (car (verilog-library-filenames + (match-string 1) (buffer-file-name)))))) + )) + + +;; ;; Bug reporting ;; ＠＠ -7490,6 +8204,7 ＠＠ verilog-auto-hook verilog-auto-indent-on-newline verilog-auto-inst-vector + verilog-auto-inst-template-numbers verilog-auto-lineup verilog-auto-newline verilog-auto-save-policy