Reanimating verilog-mode

Hi all Verilog-mode in our prog-modes package dates back to 2005. Since I tend to use the upstream version, I never noticed. I'd love to integrate the latest version (and monitor future upstream changes -- in case you would ask, Stephen). It looks like there are only few package specific changes in the code but unfortunately, I don't have access to the original sources from which the package has been created to see what exactly has been changed. Regards Marcus -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) _______________________________________________ XEmacs-Beta mailing list XEmacs-Beta(a)xemacs.org http://calypso.tux.org/cgi-bin/mailman/listinfo/xemacs-beta