6:51 p.m.
The above template will convert:
psm_mas ms2m (/*AUTOINST*/);
Typing \\[verilog-auto] will make this into:
psm_mas ms2m (/*AUTOINST*/
// Outputs
.PO_PSM_PFRAME_L (PO_PSM_PFRAME_L),
.INSTDATAOUT (INSTDATAOUT2),
.PTL_MAPVALIDX (PTL_MAPVALID[2]),
.PTL_MAPVALIDP1X (PTL_MAPVALID[3]),
....
// Inputs
....
.INSTDATA (INSTDATA[2]),
.PI_PPAR64_L (PI_PPAR64_L));
Note the ＠ character was replaced with the 2 from \"ms2m\". Also, if a
signal wasn't in the template, it is assumed to be a direct connection.
"
(save-excursion
;; Find beginning
(let ((pt (point))
(indent-pt (save-excursion
(or (and (search-backward "(" nil t) (1+ (current-column)))
(current-indentation))))
submod submodi inst tpl-list tpl-num)
;; Find module name that is instantiated
(setq submod (verilog-read-inst-module)
inst (verilog-read-inst-name))
;; Lookup position, etc of submodule
;; Note this may raise an error
(when (setq submodi (verilog-modi-lookup submod t))
;; If there's a number in the instantiation, it may be a argument to the
;; automatic variable instantiation program.
(setq tpl-num (if (string-match "[0-9]+" inst)
(substring inst (match-beginning 0) (match-end 0))
"")
tpl-list (verilog-read-auto-template submod))
;; Find submodule's signals and dump
(insert "\n")
(let ((sig-list (verilog-modi-get-outputs submodi)))
(indent-to indent-pt)
(insert "// Outputs\n") ;; Note these are searched for in
verilog-read-sub-decl
(mapcar (function (lambda (port)
(verilog-auto-inst-port port indent-pt tpl-list tpl-num)))
sig-list))
(let ((sig-list (verilog-modi-get-inouts submodi)))
(when sig-list
(indent-to indent-pt)
(insert "// Inouts\n")
(mapcar (function (lambda (port)
(verilog-auto-inst-port port indent-pt tpl-list tpl-num)))
sig-list)))
(let ((sig-list (verilog-modi-get-inputs submodi)))
(indent-to indent-pt)
(insert "// Inputs\n")
(mapcar (function (lambda (port)
(verilog-auto-inst-port port indent-pt tpl-list tpl-num)))
sig-list))
;; Kill extra semi
(save-excursion
(when (re-search-backward "," pt t)
(delete-char 1)
(insert ");")
(search-forward "\n") ;; Added by inst-port
(delete-backward-char 1)
(if (search-forward ")" nil t) ;; From user, moved up a line
(delete-backward-char 1))
(if (search-forward ";" nil t) ;; Don't error if user had syntax error
and forgot it
(delete-backward-char 1))
))
))))
(defun verilog-auto-reg ()
"Make register statements for any output that isn't already declared,
and isn't a wire output from a block.
Limitiations:
This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decl).
This does NOT work on memories, declare those yourself.
A simple example:
module ex_reg (o,i)
output o;
input i;
/*AUTOREG*/
always o <= i;
endmodule
Typing \\[verilog-auto] will make this into:
module a ()
output a;
input i;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg a;
// End of automatics
always a <= i;
endmodule
"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
(modi (verilog-modi-current))
(sig-list (verilog-signals-not-in
(verilog-modi-get-outputs modi)
(append (verilog-modi-get-wires modi)
(verilog-modi-get-regs modi)
(verilog-modi-get-assigns modi)
(verilog-modi-get-consts modi)
(verilog-modi-get-sub-outputs modi)
(verilog-modi-get-sub-inouts modi)
))))
(forward-line 1)
(indent-to indent-pt)
(insert "// Beginning of automatic regs (for this module's undeclared
outputs)\n")
(verilog-insert-definition sig-list "reg" indent-pt)
(verilog-modi-cache-add-regs modi sig-list)
(indent-to indent-pt)
(insert "// End of automatics\n")
)))
(defun verilog-auto-wire ()
"Make wire statements for outputs of instantiations that aren't already
declared.
Limitiations:
This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decl).
This does NOT work on memories, declare those yourself.
A simple example (see verilog-auto-inst for what else is going on here):
module ex_wire (o,i)
output o;
input i;
/*AUTOWIRE*/
inst inst (/*AUTOINST*/);
endmodule
Typing \\[verilog-auto] will make this into:
module ex_wire (o,i)
output o;
input i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] ov; // From inst of inst.v
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.ov (ov[31:0]),
// Inputs
.i (i));
wire o = | ov;
endmodule
"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
(modi (verilog-modi-current))
(sig-list (verilog-signals-combine-bus
(verilog-signals-not-in
(append (verilog-modi-get-sub-outputs modi)
(verilog-modi-get-sub-inouts modi))
(verilog-modi-get-signals modi)
))))
(forward-line 1)
(indent-to indent-pt)
(insert "// Beginning of automatic wires (for undeclared instantiated-module
outputs)\n")
(verilog-insert-definition sig-list "wire" indent-pt)
(verilog-modi-cache-add-wires modi sig-list)
(indent-to indent-pt)
(insert "// End of automatics\n")
)))
(defun verilog-auto-output ()
"Make output statements for any output signal from an /*AUTOINST*/ that
isn't used elsewhere inside the module. This is useful for modules which
only instantiate other modules.
Limitiations:
This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decl).
If any concatenation, or bitsubscripts are missing in the AUTOINSTant's
instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
A simple example (see verilog-auto-inst for what else is going on here):
module ex_output (ov,i)
input i;
/*AUTOWIRE*/
inst inst (/*AUTOINST*/);
endmodule
Typing \\[verilog-auto] will make this into:
module ex_output (ov,i)
input i;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] ov; // From inst of inst.v
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.ov (ov[31:0]),
// Inputs
.i (i));
endmodule
"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
(modi (verilog-modi-current))
(sig-list (verilog-signals-not-in
(verilog-modi-get-sub-outputs modi)
(append (verilog-modi-get-outputs modi)
(verilog-modi-get-inouts modi)
(verilog-modi-get-sub-inputs modi)
(verilog-modi-get-sub-inouts modi)
))))
(forward-line 1)
(indent-to indent-pt)
(insert "// Beginning of automatic outputs (from unused autoinst
outputs)\n")
(verilog-insert-definition sig-list "output" indent-pt)
(verilog-modi-cache-add-outputs modi sig-list)
(indent-to indent-pt)
(insert "// End of automatics\n")
)))
(defun verilog-auto-output-every ()
"Make output statements for any signals that aren't primary inputs or
outputs already. This makes every signal in the design a output. This is
useful to get Synopsys to preserve every signal in the design, since it
won't optimize away the outputs.
A simple example:
module ex_output_every (o,i,tempa,tempb)
output o;
input i;
/*AUTOOUTPUTEVERY*/
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule
Typing \\[verilog-auto] will make this into:
module ex_output_every (o,i,tempa,tempb)
output o;
input i;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output tempb;
output tempa;
// End of automatics
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule
"
(save-excursion
;;Point must be at insertion point
(let* ((indent-pt (current-indentation))
(modi (verilog-modi-current))
(sig-list (verilog-signals-not-in
(verilog-modi-get-signals modi)
(verilog-modi-get-ports modi)
)))
(forward-line 1)
(indent-to indent-pt)
(insert "// Beginning of automatic outputs (every signal)\n")
(verilog-insert-definition sig-list "output" indent-pt)
(verilog-modi-cache-add-outputs modi sig-list)
(indent-to indent-pt)
(insert "// End of automatics\n")
)))
(defun verilog-auto-input ()
"Make input statements for any input signal into an /*AUTOINST*/ that
isn't declared elsewhere inside the module. This is useful for modules which
only instantiate other modules.
Limitiations:
This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decl).
If any concatenation, or bitsubscripts are missing in the AUTOINSTant's
instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
A simple example (see verilog-auto-inst for what else is going on here):
module ex_input (ov,i)
output [31:0] ov;
/*AUTOINPUT*/
inst inst (/*AUTOINST*/);
endmodule
Typing \\[verilog-auto] will make this into:
module ex_input (ov,i)
output [31:0] ov;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i; // From inst of inst.v
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.ov (ov[31:0]),
// Inputs
.i (i));
endmodule
"
(save-excursion
(let* ((indent-pt (current-indentation))
(modi (verilog-modi-current))
(sig-list (verilog-signals-not-in
(verilog-modi-get-sub-inputs modi)
(append (verilog-modi-get-inputs modi)
(verilog-modi-get-inouts modi)
(verilog-modi-get-wires modi)
(verilog-modi-get-regs modi)
(verilog-modi-get-consts modi)
(verilog-modi-get-sub-outputs modi)
(verilog-modi-get-sub-inouts modi)
))))
(forward-line 1)
(indent-to indent-pt)
(insert "// Beginning of automatic inputs (from unused autoinst
inputs)\n")
(verilog-insert-definition sig-list "input" indent-pt)
(verilog-modi-cache-add-inputs modi sig-list)
(indent-to indent-pt)
(insert "// End of automatics\n")
)))
(defun verilog-auto-inout-module ()
"Take input/output/inout statements from the specified module and insert into
the current module. This is useful for making null templates and shell modules
which need to have identical I/O with another module. Any I/O which are already
defined in this module will not be redefined.
Limitiations:
Concatencation and outputting partial busses is not supported.
Module names must be resolvable to filenames. See \\[verilog-auto-inst] for help.
Signals are not inserted in the same order as in the original module, though they
will appear to be in the same order to a AUTOINST instantiating either module.
A simple example:
module ex_shell (/*AUTOARG*/)
/*AUTOINOUTMODULE(\"ex_main\")*/
endmodule
module ex_main (i,o,io)
input i;
output o;
inout io;
endmodule
Typing \\[verilog-auto] will make this into:
module ex_shell (/*AUTOARG*/i,o,io)
/*AUTOINOUTMODULE(\"ex_main\")*/
// Beginning of automatic in/out/inouts (from specific module)
input i;
output o;
inout io;
// End of automatics
endmodule
"
(save-excursion
(let* ((submod (verilog-read-auto-param)) submodi)
;; Lookup position, etc of co-module
;; Note this may raise an error
(when (setq submodi (verilog-modi-lookup submod t))
(let* ((indent-pt (current-indentation))
(modi (verilog-modi-current))
(sig-list-i (verilog-signals-not-in
(verilog-modi-get-inputs submodi)
(append (verilog-modi-get-inputs modi))))
(sig-list-o (verilog-signals-not-in
(verilog-modi-get-outputs submodi)
(append (verilog-modi-get-outputs modi))))
(sig-list-io (verilog-signals-not-in
(verilog-modi-get-inouts submodi)
(append (verilog-modi-get-inouts modi)))))
(forward-line 1)
(indent-to indent-pt)
(insert "// Beginning of automatic in/out/inouts (from specific module)\n")
;; Don't sort them so a upper AUTOINST will match the main module
(verilog-insert-definition sig-list-o "output" indent-pt t)
(verilog-insert-definition sig-list-io "inout" indent-pt t)
(verilog-insert-definition sig-list-i "input" indent-pt t)
(verilog-modi-cache-add-inputs modi sig-list-i)
(verilog-modi-cache-add-outputs modi sig-list-o)
(verilog-modi-cache-add-inouts modi sig-list-io)
(indent-to indent-pt)
(insert "// End of automatics\n")
)))))
(defun verilog-auto-sense ()
"Replace the always (/*AUTOSENSE*/) sensitivity list with one
automatically derived from all inputs declared in the always statement.
Signals that are generated within the same always block are NOT placed into
the sensitivity list (see verilog-auto-sense-include-inputs).
Long lines are split based on the fill-column, see \\[set-fill-column].
Limitiations:
The end of a always is considered to be a ; unless a begin/end is used.
This is wrong for \"always if foo else bar\", so use begin/end pairs
after always!
Verilog does not allow memories (multidimensional arrays) in sensitivity
lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
Constant signals:
AUTOSENSE cannot always determine if a `define is a constant or a signal
(it could be in a include file for example). If a `define or other signal
is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
declaration anywhere in the module (parenthesis are required):
/* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
Better yet, use a parameter, which will be understood to be constant
automatically.
OOps!
If AUTOSENSE makes a mistake, please report it. As a workaround, if
a signal that shouldn't be in the sensitivity list was, use the
AUTO_CONSTANT above. If a signal should be in the sensitivity list
wasn't, placing it before the /*AUTOSENSE*/ comment will prevent it from
being deleted when the autos are updated.
A simple example:
always ＠ (/*AUTOSENSE*/) begin
/* AUTO_CONSTANT (`constant) */
outin <= ina | inb | `constant;
out <= outin;
end
Typing \\[verilog-auto] will make this into:
always ＠ (/*AUTOSENSE*/ina or inb) begin
/* AUTO_CONSTANT (`constant) */
outin <= ina | inb | `constant;
out <= outin;
end
"
(save-excursion
;; Find beginning
(let* ((indent-pt (save-excursion
(or (and (search-backward "(" nil t) (1+ (current-column)))
(current-indentation))))
(modi (verilog-modi-current))
(sig-memories (verilog-signals-memory (verilog-modi-get-regs modi)))
sigss sig-list not-first)
;; Read signals in always, eliminate outputs from sense list
(setq sigss (verilog-read-always-signals))
(setq sig-list (verilog-signals-not-in (nth 0 sigss)
(append (and (not verilog-auto-sense-include-inputs) (nth 1 sigss))
(verilog-modi-get-consts modi))
))
(when sig-memories
(let ((tlen (length sig-list)))
(setq sig-list (verilog-signals-not-in sig-list sig-memories))
(if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
(setq sig-list (sort sig-list (function (lambda (a b) (string< (car a) (car
b))))))
(while sig-list
(cond ((> (+ 4 (current-column) (length (nth 0 (car sig-list)))) fill-column) ;+4 for
width of or
(insert "\n")
(indent-to indent-pt)
(if not-first (insert "or ")))
(not-first (insert " or ")))
(insert (nth 0 (car sig-list)))
(setq sig-list (cdr sig-list)
not-first t))
)))
;;;
;;; Auto top level
;;;
(defun verilog-auto ()
"Look for any /*AUTO...*/ commands in the code, as used in
instantiations or argument headers. Update the list of signals
following the /*AUTO...*/ command.
Use \\[verilog-delete-auto] to remove the AUTOs.
The hooks verilog-before-auto-hook and verilog-auto-hook are
called before and after this function, respectively.
For example:
module (/*AUTOARG*/)
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*AUTOREG*/
somesub sub (/*AUTOINST*/);
Using \\[describe-function], see also:
verilog-auto-arg for AUTOARG module instantiations
verilog-auto-inst for AUTOINST argument declarations
verilog-auto-input for AUTOINPUT making hiearchy inputs
verilog-auto-output for AUTOOUTPUT making hiearchy outputs
verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
verilog-auto-wire for AUTOWIRE instantiation wires
verilog-auto-reg for AUTOREG registers
verilog-auto-sense for AUTOSENSE always sensitivity lists
verilog-read-defines for reading `define values
If you have bugs with these autos, try contacting
Wilson Snyder (wsnyder(a)world.std.com)
"
(interactive)
(message "Updating AUTOs...")
(if (featurep 'dinotrace)
(dinotrace-unannotate-all))
(let ((oldbuf (if (not (buffer-modified-p))
(buffer-string)))
;; Before version 20, match-string with font-lock returns a
;; vector that is not equal to the string. IE if on "input"
;; nil==(equal "input" (progn (looking-at "input") (match-string
0)))
(fontlocked (when (and (memq 'v19 verilog-emacs-features)
(boundp 'font-lock-mode)
font-lock-mode)
(font-lock-mode nil)
t)))
(save-excursion
(run-hooks 'verilog-before-auto-hook)
;; This particular ordering is important
;; INST: Lower modules correct, no internal dependencies, FIRST
(verilog-preserve-cache
;; Clear existing autos else we'll be screwed by existing ones
(verilog-delete-auto)
;;
(verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
;; Doesn't matter when done, but combine it with a common changer
(verilog-auto-search-do "/*AUTOSENSE*/" 'verilog-auto-sense))
;;
;; Inputs/outputs are mutually independant
(verilog-preserve-cache
;; first in/outs from other files
(verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/"
'verilog-auto-inout-module)
;; next in/outs which need previous sucked inputs first
(verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output)
(verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input)
;; outputevery needs autooutputs done first
(verilog-auto-search-do "/*AUTOOUTPUTEVERY*/"
'verilog-auto-output-every)
;; Wires/regs must be after inputs/outputs
(verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
(verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
;; Must be after all inputs outputs are generated
(verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
)
;;
(run-hooks 'verilog-auto-hook)
;;
;; If end result is same as when started, clear modified flag
(cond ((and oldbuf (equal oldbuf (buffer-string)))
(set-buffer-modified-p nil)
(message "Updating AUTOs...done (no changes)"))
(t (message "Updating AUTOs...done")))
;; Restore font-lock
(when fontlocked (font-lock-mode t))
)))
;;;
;;; Bug reporting
;;;
(defun verilog-submit-bug-report ()
"Submit via mail a bug report on lazy-lock.el."
(interactive)
(let ((reporter-prompt-for-summary-p t))
(reporter-submit-bug-report
"verilog-mode-bugs(a)surefirev.com"
(concat "verilog-mode v" (substring verilog-mode-version 12 -3))
'(verilog-indent-level
verilog-indent-level-module
verilog-indent-level-declaration
verilog-indent-level-behavioral
verilog-cexp-indent
verilog-case-indent
verilog-auto-newline
verilog-auto-indent-on-newline
verilog-tab-always-indent
verilog-auto-endcomments
verilog-minimum-comment-distance
verilog-indent-begin-after-if
verilog-auto-lineup)
nil nil
(concat "Hi Mac,
I want to report a bug. I've read the `Bugs' section of `Info' on
Emacs, so I know how to make a clear and unambiguous report. To get
to that Info section, I typed
M-x info RET m " invocation-name " RET m bugs RET
Before I go further, I want to say that Verilog mode has changed my life.
I save so much time, my files are colored nicely, my co workers respect
my coding ability... until now. I'd really appreciate anything you
could do to help me out with this minor deficiency in the product.
To reproduce the bug, start a fresh Emacs via " invocation-name "
-no-init-file -no-site-file'. In a new buffer, in verilog mode, type
the code included below.
Given those lines, I expected [[Fill in here]] to happen;
but instead, [[Fill in here]] happens!.
== The code: =="))))
;;; verilog.el ends here