CVS update by james MODIFIED: packages/xemacs-packages/vhdl, vhdl-mode.el ...

User: james Date: 05/02/14 18:27:52 Modified: packages/xemacs-packages/vhdl ChangeLog Makefile vhdl-mode.el Log: Update to upstream version 3.33.2. See xemacs-patches message with ID <psy8e0ca6k.fsf(a)diannao.ittc.ku.edu&gt;. Revision Changes Path 1.24 +5 -0 XEmacs/packages/xemacs-packages/vhdl/ChangeLog Index: ChangeLog =================================================================== RCS file: /pack/xemacscvs/XEmacs/packages/xemacs-packages/vhdl/ChangeLog,v retrieving revision 1.23 retrieving revision 1.24 diff -u -r1.23 -r1.24 --- ChangeLog 2004/03/18 16:56:20 1.23 +++ ChangeLog 2005/02/14 17:27:50 1.24 ＠＠ -1,3 +1,8 ＠＠ +2005-02-07 Jerry James <james(a)xemacs.org&gt; + + * vhdl-mode.el: Sync with version 3.33.2. + * Makefile (AUTHOR_VERSION): Change to 3.33.2. + 2004-03-18 Norbert Koch <viteno(a)xemacs.org&gt; * Makefile (VERSION): XEmacs package 1.19 released. 1.29 +1 -1 XEmacs/packages/xemacs-packages/vhdl/Makefile Index: Makefile =================================================================== RCS file: /pack/xemacscvs/XEmacs/packages/xemacs-packages/vhdl/Makefile,v retrieving revision 1.28 retrieving revision 1.29 diff -u -r1.28 -r1.29 --- Makefile 2004/03/18 16:56:20 1.28 +++ Makefile 2005/02/14 17:27:50 1.29 ＠＠ -18,7 +18,7 ＠＠ # Boston, MA 02111-1307, USA. VERSION = 1.19 -AUTHOR_VERSION = 3.32.20 +AUTHOR_VERSION = 3.33.2 MAINTAINER = XEmacs Development Team <xemacs-beta(a)xemacs.org&gt; PACKAGE = vhdl PKG_TYPE = regular 1.8 +594 -290 XEmacs/packages/xemacs-packages/vhdl/vhdl-mode.el Index: vhdl-mode.el =================================================================== RCS file: /pack/xemacscvs/XEmacs/packages/xemacs-packages/vhdl/vhdl-mode.el,v retrieving revision 1.7 retrieving revision 1.8 diff -u -r1.7 -r1.8 --- vhdl-mode.el 2004/03/18 16:25:09 1.7 +++ vhdl-mode.el 2005/02/14 17:27:50 1.8 ＠＠ -1,18 +1,18 ＠＠ ;;; vhdl-mode.el --- major mode for editing VHDL code -;; Copyright (C) 1992-2003 Free Software Foundation, Inc. +;; Copyright (C) 1992-2005 Free Software Foundation, Inc. ;; Authors: Reto Zimmermann <reto(a)gnu.org&gt; ;; Rodney J. Whitby <software.vhdl-mode(a)rwhitby.net&gt; ;; Maintainer: Reto Zimmermann <reto(a)gnu.org&gt; -;; RCS: $Id: vhdl-mode.el,v 1.7 2004/03/18 16:25:09 james Exp $ +;; RCS: $Id: vhdl-mode.el,v 1.8 2005/02/14 17:27:50 james Exp $ ;; Keywords: languages vhdl ;; WWW: http://opensource.ethz.ch/emacs/vhdl-mode.html -(defconst vhdl-version "3.32.20" +(defconst vhdl-version "3.33.2" "VHDL Mode version number.") -(defconst vhdl-time-stamp "2004-02-16" +(defconst vhdl-time-stamp "2005-01-11" "VHDL Mode time stamp for last update.") ;; This file is part of GNU Emacs. ＠＠ -45,6 +45,8 ＠＠ ;; - Insertion of file headers ;; - Insertion of user-specified models ;; - Port translation / testbench generation +;; - Structural composition +;; - Configuration generation ;; - Sensitivity list updating ;; - File browser ;; - Design hierarchy browser ＠＠ -750,15 +752,28 ＠＠ "*Specifies how the architecture file name is obtained. The architecture file name can be obtained by modifying the entity and/or architecture name (e.g. attaching or stripping off a substring). The -string that is matched against the regexp is the concatenation of the entity -and the architecture name separated by a space. This gives access to both -names (see default setting as example)." +file extension is automatically taken from the file name of the current +buffer. The string that is matched against the regexp is the concatenation +of the entity and the architecture name separated by a space. This gives +access to both names (see default setting as example)." vhdl-name-doc-string) :type '(cons (regexp :tag "From regexp") (string :tag "To string ")) :group 'vhdl-naming :group 'vhdl-compose) +(defcustom vhdl-configuration-file-name '(".*" . "\\&") + (concat + "*Specifies how the configuration file name is obtained. +The configuration file name can be obtained by modifying the configuration +name (e.g. attaching or stripping off a substring). The file extension is +automatically taken from the file name of the current buffer." + vhdl-name-doc-string) + :type '(cons (regexp :tag "From regexp") + (string :tag "To string ")) + :group 'vhdl-naming + :group 'vhdl-compose) + (defcustom vhdl-package-file-name '(".*" . "\\&") (concat "*Specifies how the package file name is obtained. ＠＠ -1082,6 +1097,99 ＠＠ :group 'vhdl-model) +(defgroup vhdl-compose nil + "Customizations for structural composition." + :group 'vhdl) + +(defcustom vhdl-compose-architecture-name '(".*" . "str") + (concat + "*Specifies how the component architecture name is obtained. +The component architecture name can be obtained by modifying the entity name +\(e.g. attaching or stripping off a substring). +If TO STRING is empty, the architecture name is queried." + vhdl-name-doc-string) + :type '(cons (regexp :tag "From regexp") + (string :tag "To string ")) + :group 'vhdl-compose) + +(defcustom vhdl-compose-configuration-name + '("\\(.*\\) \\(.*\\)" . "\\1_\\2_cfg") + (concat + "*Specifies how the configuration name is obtained. +The configuration name can be obtained by modifying the entity and/or +architecture name (e.g. attaching or stripping off a substring). The string +that is matched against the regexp is the concatenation of the entity and the +architecture name separated by a space. This gives access to both names (see +default setting as example)." + vhdl-name-doc-string) + :type '(cons (regexp :tag "From regexp") + (string :tag "To string ")) + :group 'vhdl-compose) + +(defcustom vhdl-components-package-name + '((".*" . "\\&_components") . "components") + (concat + "*Specifies how the name for the components package is obtained. +The components package is a package containing all component declarations for +the current design. It's name can be obtained by modifying the project name +\(e.g. attaching or stripping off a substring). If no project is defined, the +DIRECTORY entry is chosen." + vhdl-name-doc-string) + :type '(cons (cons :tag "Project" :indent 2 + (regexp :tag "From regexp") + (string :tag "To string ")) + (string :tag "Directory:\n String ")) + :group 'vhdl-compose) + +(defcustom vhdl-use-components-package nil + "*Non-nil means use a separate components package for component declarations. +Otherwise, component declarations are inserted and searched for in the +architecture declarative parts." + :type 'boolean + :group 'vhdl-compose) + +(defcustom vhdl-compose-include-header t + "*Non-nil means include a header in automatically generated files." + :type 'boolean + :group 'vhdl-compose) + +(defcustom vhdl-compose-create-files 'single + "*Specifies whether new files should be created for the new component. +The component's entity and architecture are inserted: + None : in current buffer + Single file : in new single file + Separate files: in two separate files +The file names are obtained from variables `vhdl-entity-file-name' and +`vhdl-architecture-file-name'." + :type '(choice (const :tag "None" none) + (const :tag "Single file" single) + (const :tag "Separate files" separate)) + :group 'vhdl-compose) + +(defcustom vhdl-compose-configuration-create-file nil + "*Specifies whether a new file should be created for the configuration. +If non-nil, a new file is created for the configuration. +The file name is obtained from variable `vhdl-configuration-file-name'." + :type 'boolean + :group 'vhdl-compose) + +(defcustom vhdl-compose-configuration-hierarchical t + "*Specifies whether hierarchical configurations should be created. +If non-nil, automatically created configurations are hierarchical and include +the whole hierarchy of subcomponents. Otherwise the configuration only +includes one level of subcomponents." + :type 'boolean + :group 'vhdl-compose) + +(defcustom vhdl-compose-configuration-use-subconfiguration t + "*Specifies whether subconfigurations should be used inside configurations. +If non-nil, automatically created configurations use configurations in binding +indications for subcomponents, if such configurations exist. Otherwise, +entities are used in binding indications for subcomponents." + :type 'boolean + :group 'vhdl-compose) + + (defgroup vhdl-port nil "Customizations for port translation functions." :group 'vhdl ＠＠ -1161,8 +1269,7 ＠＠ (string :tag "To string ")) :group 'vhdl-testbench) -(defcustom vhdl-testbench-configuration-name - '("\\(.*\\) \\(.*\\)" . "\\1_\\2_cfg") +(defcustom vhdl-testbench-configuration-name vhdl-compose-configuration-name (concat "*Specifies how the testbench configuration name is obtained. The configuration name of a testbench can be obtained by modifying the entity ＠＠ -1280,62 +1387,6 ＠＠ :group 'vhdl-testbench) -(defgroup vhdl-compose nil - "Customizations for structural composition." - :group 'vhdl) - -(defcustom vhdl-compose-create-files 'single - "*Specifies whether new files should be created for the new component. -The component's entity and architecture are inserted: - None : in current buffer - Single file : in new single file - Separate files: in two separate files -The file names are obtained from variables `vhdl-entity-file-name' and -`vhdl-architecture-file-name'." - :type '(choice (const :tag "None" none) - (const :tag "Single file" single) - (const :tag "Separate files" separate)) - :group 'vhdl-compose) - -(defcustom vhdl-compose-include-header t - "*Non-nil means include a header in automatically generated files." - :type 'boolean - :group 'vhdl-compose) - -(defcustom vhdl-compose-architecture-name '(".*" . "str") - (concat - "*Specifies how the component architecture name is obtained. -The component architecture name can be obtained by modifying the entity name -\(e.g. attaching or stripping off a substring). -If TO STRING is empty, the architecture name is queried." - vhdl-name-doc-string) - :type '(cons (regexp :tag "From regexp") - (string :tag "To string ")) - :group 'vhdl-compose) - -(defcustom vhdl-components-package-name - '((".*" . "\\&_components") . "components") - (concat - "*Specifies how the name for the components package is obtained. -The components package is a package containing all component declarations for -the current design. Its name can be obtained by modifying the project name -\(e.g. attaching or stripping off a substring). If no project is defined, the -DIRECTORY entry is chosen." - vhdl-name-doc-string) - :type '(cons (cons :tag "Project" :indent 2 - (regexp :tag "From regexp") - (string :tag "To string ")) - (string :tag "Directory:\n String ")) - :group 'vhdl-compose) - -(defcustom vhdl-use-components-package nil - "*Non-nil means use a separate components package for component declarations. -Otherwise, component declarations are inserted and searched for in the -architecture declarative parts." - :type 'boolean - :group 'vhdl-compose) - - (defgroup vhdl-comment nil "Customizations for comments." :group 'vhdl) ＠＠ -1814,6 +1865,7 ＠＠ (defconst vhdl-offsets-alist-default '((string . -1000) + (cpp-macro . -1000) (block-open . 0) (block-close . 0) (statement . 0) ＠＠ -2661,6 +2713,7 ＠＠ (define-key vhdl-mode-map "\C-c\C-c\C-n" 'vhdl-compose-new-component) (define-key vhdl-mode-map "\C-c\C-c\C-p" 'vhdl-compose-place-component) (define-key vhdl-mode-map "\C-c\C-c\C-w" 'vhdl-compose-wire-components) + (define-key vhdl-mode-map "\C-c\C-c\C-f" 'vhdl-compose-configuration) (define-key vhdl-mode-map "\C-c\C-c\C-k" 'vhdl-compose-components-package) (define-key vhdl-mode-map "\C-cc" 'vhdl-comment-uncomment-region) (define-key vhdl-mode-map "\C-c-" 'vhdl-comment-append-inline) ＠＠ -3308,9 +3361,11 ＠＠ :style toggle :selected vhdl-port-reversed-direction :active vhdl-port-list]) ("Compose" ["New Component" vhdl-compose-new-component t] + ["Copy Component" vhdl-port-copy t] ["Place Component" vhdl-compose-place-component vhdl-port-list] ["Wire Components" vhdl-compose-wire-components t] "--" + ["Generate Configuration" vhdl-compose-configuration t] ["Generate Components Package" vhdl-compose-components-package t]) ("Subprogram" ["Copy" vhdl-subprog-copy t] ＠＠ -3554,6 +3609,8 ＠＠ ["Entity File Name..." (customize-option 'vhdl-entity-file-name) t] ["Architecture File Name..." (customize-option 'vhdl-architecture-file-name) t] + ["Configuration File Name..." + (customize-option 'vhdl-configuration-file-name) t] ["Package File Name..." (customize-option 'vhdl-package-file-name) t] ("File Name Case" ["As Is" ＠＠ -3731,7 +3788,21 ＠＠ "--" ["Customize Group..." (customize-group 'vhdl-port) t]) ("Compose" - ("Create Files" + ["Architecture Name..." + (customize-option 'vhdl-compose-architecture-name) t] + ["Configuration Name..." + (customize-option 'vhdl-compose-configuration-name) t] + ["Components Package Name..." + (customize-option 'vhdl-components-package-name) t] + ["Use Components Package" + (customize-set-variable 'vhdl-use-components-package + (not vhdl-use-components-package)) + :style toggle :selected vhdl-use-components-package] + ["Include Header" + (customize-set-variable 'vhdl-compose-include-headera + (not vhdl-compose-include-header)) + :style toggle :selected vhdl-compose-include-header] + ("Create Entity/Architecture Files" ["None" (customize-set-variable 'vhdl-compose-create-files 'none) :style radio :selected (eq 'none vhdl-compose-create-files)] ＠＠ -3741,18 +3812,18 ＠＠ ["Separate" (customize-set-variable 'vhdl-compose-create-files 'separate) :style radio :selected (eq 'separate vhdl-compose-create-files)]) - ["Include Header" - (customize-set-variable 'vhdl-compose-include-header - (not vhdl-compose-include-header)) - :style toggle :selected vhdl-compose-include-header] - ["Architecture Name..." - (customize-option 'vhdl-compose-architecture-name) t] - ["Components Package Name..." - (customize-option 'vhdl-components-package-name) t] - ["Use Components Package" - (customize-set-variable 'vhdl-use-components-package - (not vhdl-use-components-package)) - :style toggle :selected vhdl-use-components-package] + ["Create Configuration File" + (customize-set-variable 'vhdl-compose-configuration-create-file + (not vhdl-compose-configuration-create-file)) + :style toggle :selected vhdl-compose-configuration-create-file] + ["Hierarchical Configuration" + (customize-set-variable 'vhdl-compose-configuration-hierarchical + (not vhdl-compose-configuration-hierarchical)) + :style toggle :selected vhdl-compose-configuration-hierarchical] + ["Use Subconfiguration" + (customize-set-variable 'vhdl-compose-configuration-use-subconfiguration + (not vhdl-compose-configuration-use-subconfiguration)) + :style toggle :selected vhdl-compose-configuration-use-subconfiguration] "--" ["Customize Group..." (customize-group 'vhdl-compose) t]) ("Comment" ＠＠ -4203,13 +4274,13 ＠＠ symbols are surrounded by one space, and multiple spaces are eliminated. -| CODE FILLING: -| Code filling allows to condens code (e.g. sensitivity lists or port -| maps) by removing comments and newlines and re-wrapping so that all -| lines are maximally filled (block filling). `C-c C-f C-f' fills a list -| enclosed by parenthesis, `C-c C-f C-g' a group of lines separated by -| blank lines, `C-c C-f C-i' a block of lines with same indent, and -| `C-c C-f M-f' an entire region. + CODE FILLING: + Code filling allows to condens code (e.g. sensitivity lists or port + maps) by removing comments and newlines and re-wrapping so that all + lines are maximally filled (block filling). `C-c C-f C-f' fills a list + enclosed by parenthesis, `C-c C-f C-g' a group of lines separated by + blank lines, `C-c C-f C-i' a block of lines with same indent, and + `C-c C-f M-f' an entire region. CODE BEAUTIFICATION: ＠＠ -4234,21 +4305,21 ＠＠ A clause with several generic/port names on the same line can be flattened (`C-c C-p C-f') so that only one name per line exists. The -| direction of ports can be reversed (`C-c C-p C-r'), i.e., inputs become -| outputs and vice versa, which can be useful in testbenches. (This -| reversion is done on the internal data structure and is only reflected -| in subsequent paste operations.) + direction of ports can be reversed (`C-c C-p C-r'), i.e., inputs become + outputs and vice versa, which can be useful in testbenches. (This + reversion is done on the internal data structure and is only reflected + in subsequent paste operations.) Names for actual ports, instances, testbenches, and design-under-test instances can be derived from existing names according to options `vhdl-...-name'. See customization group `vhdl-port'. -| SUBPROGRAM TRANSLATION: -| Similar functionality exists for copying/pasting the interface of -| subprograms (function/procedure). A subprogram interface can be copied -| and then pasted as a subprogram declaration, body or call (uses -| association list with formals). + SUBPROGRAM TRANSLATION: + Similar functionality exists for copying/pasting the interface of + subprograms (function/procedure). A subprogram interface can be copied + and then pasted as a subprogram declaration, body or call (uses + association list with formals). TESTBENCH GENERATION: ＠＠ -4304,38 +4375,54 ＠＠ required by secondary units. -| STRUCTURAL COMPOSITION: -| Enables simple structural composition. `C-c C-c C-n' creates a skeleton -| for a new component. Subcomponents (i.e. component declaration and -| instantiation) can be automatically placed from a previously read port -| \(`C-c C-c C-p') or directly from the hierarchy browser (`P'). Finally, -| all subcomponents can be automatically connected using internal signals -| and ports (`C-c C-c C-w') following these rules: -| - subcomponent actual ports with same name are considered to be -| connected by a signal (internal signal or port) -| - signals that are only inputs to subcomponents are considered as -| inputs to this component -> input port created -| - signals that are only outputs from subcomponents are considered as -| outputs from this component -> output port created -| - signals that are inputs to AND outputs from subcomponents are -| considered as internal connections -> internal signal created -| -| Component declarations can be placed in a components package (option -| `vhdl-use-components-package') which can be automatically generated for -| an entire directory or project (`C-c C-c M-p'). The VHDL'93 direct -| component instantiation is also supported (option -| `vhdl-use-direct-instantiation'). + STRUCTURAL COMPOSITION: + Enables simple structural composition. `C-c C-c C-n' creates a skeleton + for a new component. Subcomponents (i.e. component declaration and + instantiation) can be automatically placed from a previously read port + \(`C-c C-c C-p') or directly from the hierarchy browser (`P'). Finally, + all subcomponents can be automatically connected using internal signals + and ports (`C-c C-c C-w') following these rules: + - subcomponent actual ports with same name are considered to be + connected by a signal (internal signal or port) + - signals that are only inputs to subcomponents are considered as + inputs to this component -> input port created + - signals that are only outputs from subcomponents are considered as + outputs from this component -> output port created + - signals that are inputs to AND outputs from subcomponents are + considered as internal connections -> internal signal created + + Purpose: With appropriate naming conventions it is possible to + create higher design levels with only a few mouse clicks or key + strokes. A new design level can be created by simply generating a new + component, placing the required subcomponents from the hierarchy + browser, and wiring everything automatically. + + Note: Automatic wiring only works reliably on templates of new + components and component instantiations that were created by VHDL mode. + + Component declarations can be placed in a components package (option + `vhdl-use-components-package') which can be automatically generated for + an entire directory or project (`C-c C-c M-p'). The VHDL'93 direct + component instantiation is also supported (option + `vhdl-use-direct-instantiation'). + +| Configuration declarations can automatically be generated either from +| the menu (`C-c C-c C-f') (for the architecture the cursor is in) or from +| the speedbar menu (for the architecture under the cursor). The +| configurations can optionally be hierarchical (i.e. include all +| component levels of a hierarchical design, option +| `vhdl-compose-configuration-hierarchical') or include subconfigurations +| (option `vhdl-compose-configuration-use-subconfiguration'). For +| subcomponents in hierarchical configurations, the most-recently-analyzed +| (mra) architecture is selected. If another architecture is desired, it +| can be marked as most-recently-analyzed (speedbar menu) before +| generating the configuration. | -| Purpose: With appropriate naming conventions it is possible to -| create higher design levels with only a few mouse clicks or key -| strokes. A new design level can be created by simply generating a new -| component, placing the required subcomponents from the hierarchy -| browser, and wiring everything automatically. -| -| Note: Automatic wiring only works reliably on templates of new -| components and component instantiations that were created by VHDL mode. -| -| See the options group `vhdl-compose' for all relevant user options. +| Note: Configurations of subcomponents (i.e. hierarchical configuration +| declarations) are currently not considered when displaying +| configurations in speedbar. + + See the options group `vhdl-compose' for all relevant user options. SOURCE FILE COMPILATION: ＠＠ -5266,6 +5353,7 ＠＠ (cond ((nth 3 state) 'string) ((nth 4 state) 'comment) + ((vhdl-beginning-of-macro) 'pound) (t nil))))) (defun vhdl-forward-comment (&optional direction) ＠＠ -5348,15 +5436,20 ＠＠ (defun vhdl-forward-syntactic-ws (&optional lim) "Forward skip of syntactic whitespace." - (save-restriction - (let* ((lim (or lim (point-max))) - (here lim) - (hugenum (point-max))) - (narrow-to-region lim (point)) - (while (/= here (point)) - (setq here (point)) - (vhdl-forward-comment hugenum))))) + (let* ((here (point-max)) + (hugenum (point-max))) + (while (/= here (point)) + (setq here (point)) + (vhdl-forward-comment hugenum) + ;; skip preprocessor directives + (when (and (eq (char-after) ?#) + (= (vhdl-point 'boi) (point))) + (while (and (eq (char-before (vhdl-point 'eol)) ?\\) + (= (forward-line 1) 0))) + (end-of-line))) + (if lim (goto-char (min (point) lim))))) + ;; This is the best we can do in Win-Emacs. (defun vhdl-win-fsws (&optional lim) "Forward skip syntactic whitespace for Win-Emacs." ＠＠ -5373,18 +5466,28 ＠＠ (and (string-match "Win-Emacs" emacs-version) (fset 'vhdl-forward-syntactic-ws 'vhdl-win-fsws)) +(defun vhdl-beginning-of-macro (&optional lim) + "Go to the beginning of a cpp macro definition (nicked from `cc-engine')." + (let ((here (point))) + (beginning-of-line) + (while (eq (char-before (1- (point))) ?\\) + (forward-line -1)) + (back-to-indentation) + (if (and (<= (point) here) + (eq (char-after) ?#)) + t + (goto-char here) + nil))) + (defun vhdl-backward-syntactic-ws (&optional lim) "Backward skip over syntactic whitespace." - (save-restriction - (let* ((lim (or lim (point-min))) - (here lim) - (hugenum (- (point-max)))) - (if (< lim (point)) - (progn - (narrow-to-region lim (point)) - (while (/= here (point)) - (setq here (point)) - (vhdl-forward-comment hugenum))))))) + (let* ((here (point-min)) + (hugenum (- (point-max)))) + (while (/= here (point)) + (setq here (point)) + (vhdl-forward-comment hugenum) + (vhdl-beginning-of-macro)) + (if lim (goto-char (max (point) lim))))) ;; This is the best we can do in Win-Emacs. (defun vhdl-win-bsws (&optional lim) ＠＠ -6729,6 +6832,8 ＠＠ (skip-chars-forward " \t") (if (looking-at "--") (vhdl-add-syntax 'comment)) + (if (eq literal 'pound) + (vhdl-add-syntax 'cpp-macro)) ;; return the syntax vhdl-syntactic-context)))) ＠＠ -7520,7 +7625,7 ＠＠ (if (match-string 1) (goto-char (match-end 1)) (replace-match "\\3 \\4 \\5") - (goto-char (match-end 4)))) + (goto-char (match-end 2)))) ;; eliminate multiple spaces and spaces at end of line (goto-char beg) (while (or (and (looking-at "--.*\n") (re-search-forward "--.*\n" end t)) ＠＠ -7653,7 +7758,7 ＠＠ (message "Updating sensitivity lists...") (while (re-search-forward "^\\s-*\\(\\w+[ \t\n]*:[ \t\n]*\\)?process\\>" nil t) (goto-char (match-beginning 0)) - (condition-case nil (vhdl-update-sensitivity-list) (error))) + (condition-case nil (vhdl-update-sensitivity-list) (error ""))) (message "Updating sensitivity lists...done")))) (defun vhdl-update-sensitivity-list () ＠＠ -7697,8 +7802,9 ＠＠ ((re-search-forward "^\\s-*case\\>" proc-end t) (re-search-forward "\\<is\\>" proc-end t)) ;; parameter list of procedure call - ((re-search-forward "^\\s-*\\w+[ \t\n]*(" proc-end t) - (progn (backward-char) (forward-sexp) (point))))) + ((and (re-search-forward "^\\s-*\\w+[ \t\n]*(" proc-end t) + (1- (point))) + (progn (forward-sexp) (point))))) name read-list sens-list signal-list sens-beg sens-end beg end margin) ;; scan for signals in old sensitivity list ＠＠ -9681,11 +9787,14 ＠＠ (match-string 2)))) (equal (downcase library) "work")) (vhdl-insert-keyword "LIBRARY ") - (insert library ";\n") - (indent-to margin)) - (vhdl-insert-keyword "USE ") - (insert library "." package) - (vhdl-insert-keyword ".ALL;")))) + (insert library ";") + (when package + (insert "\n") + (indent-to margin))) + (when package + (vhdl-insert-keyword "USE ") + (insert library "." package) + (vhdl-insert-keyword ".ALL;"))))) (defun vhdl-template-package-math-complex () "Insert specification of `math_complex' package." ＠＠ -10763,6 +10872,7 ＠＠ string) (vhdl-forward-comment (point-max)) (setq string (buffer-substring-no-properties start (point))) + (vhdl-forward-syntactic-ws) ;; strip off leading blanks and first newline (while (string-match "^\\(\\s-+\\)" string) (setq string (concat (substring string 0 (match-beginning 1)) ＠＠ -10940,7 +11050,7 ＠＠ (while (not end-of-list) ;; parse object (setq object - (and (vhdl-parse-string "\\(signal\\|quantity\\|terminal\\)[ \t\n]*" t) + (and (vhdl-parse-string "\\<\\(signal\\|quantity\\|terminal\\)\\>[ \t\n]*" t) (match-string-no-properties 1))) ;; parse names (accept extended identifiers) (vhdl-parse-string "\\(\\w+\\|\\\\[^\\]+\\\\\\)[ \t\n]*") ＠＠ -10950,7 +11060,7 ＠＠ ;; parse direction (vhdl-parse-string ":[ \t\n]*") (setq direct - (and (vhdl-parse-string "\\(in\\|out\\|inout\\|buffer\\|linkage\\)[ \t\n]+" t) + (and (vhdl-parse-string "\\<\\(in\\|out\\|inout\\|buffer\\|linkage\\)\\>[ \t\n]+" t) (match-string-no-properties 1))) ;; parse type (vhdl-parse-string "\\([^();\n]+\\)") ＠＠ -11167,7 +11277,10 ＠＠ (car (nth 0 (car generic-list))) (or (nth 2 (car generic-list)) " "))) (setq generic-list (cdr generic-list)) - (insert (if generic-list ", " ")"))) + (insert (if generic-list ", " ")")) + (when (and (not generic-list) secondary + (null (nth 2 vhdl-port-list))) + (insert ";"))) (unless vhdl-argument-list-indent (insert "\n") (indent-to (+ margin vhdl-basic-offset))) (setq list-margin (current-column)) ＠＠ -11183,6 +11296,9 ＠＠ (or (nth 2 generic) ""))) (setq generic-list (cdr generic-list)) (insert (if generic-list "," ")")) + (when (and (not generic-list) secondary + (null (nth 2 vhdl-port-list))) + (insert ";")) ;; paste comment (when (or vhdl-include-type-comments (and vhdl-include-port-comments (nth 3 generic))) ＠＠ -11210,7 +11326,7 ＠＠ (insert (vhdl-replace-string vhdl-actual-port-name (car (nth 0 (car port-list))))) (setq port-list (cdr port-list)) - (insert (if port-list ", " ");"))) + (insert (if port-list ", " ")"))) (unless vhdl-argument-list-indent (insert "\n") (indent-to (+ margin vhdl-basic-offset))) (setq list-margin (current-column)) ＠＠ -11290,6 +11406,8 ＠＠ (when (nth 2 vhdl-port-list) (insert "\n") (indent-to (+ margin vhdl-basic-offset)) (vhdl-port-paste-port-map)) + (unless (or (nth 1 vhdl-port-list) (nth 2 vhdl-port-list)) + (insert ";")) (message "Pasting port as instantiation \"%s\"...done" name)) (setq vhdl-port-list orig-vhdl-port-list)))) ＠＠ -12241,8 +12359,7 ＠＠ (load-file file-name) (when (/= (length (aget vhdl-project-alist vhdl-project t)) 10) (adelete 'vhdl-project-alist vhdl-project) - ;; XEmacs change: we do not support a no-args (error) - (error "Internal VHDL mode error.")) + (error "")) (when not-make-current (setq vhdl-project current-project)) (vhdl-update-mode-menu) ＠＠ -12499,7 +12616,7 ＠＠ "postponed\\|process\\|" (when (vhdl-standard-p 'ams) "procedural\\|") "with\\|while" - "\\)\\>\\|\\w+\\s-*\\(([^\n]*)\\)*\\s-*<=\\)") + "\\)\\>\\|\\w+\\s-*\\(([^\n]*)\\|\\.\\w+\\)*\\s-*<=\\)") 1 'font-lock-function-name-face) ;; highlight label and component name of component instantiations ＠＠ -12758,14 +12875,18 ＠＠ (defun vhdl-font-lock-init () "Initialize fontification." - ;; highlight template prompts and directives + ;; highlight template prompts and directives (setq vhdl-font-lock-keywords-0 (list (list (concat "\\(^\\|[ \t(.']\\)\\(<" vhdl-template-prompt-syntax ">\\)") 2 'vhdl-font-lock-prompt-face t) (list (concat "--\\s-*" vhdl-directive-keywords-regexp "\\s-+\\(.*\\)$") - 2 'vhdl-font-lock-directive-face t))) + 2 'vhdl-font-lock-directive-face t) + ;; highlight c-preprocessor directives + (list "^#[ \t]*\\(\\w+\\)\\([ \t]+\\(\\w+\\)\\)?" + '(1 font-lock-builtin-face) + '(3 font-lock-variable-name-face nil t)))) ;; highlight keywords and standardized types, attributes, enumeration ;; values, and subprograms (setq vhdl-font-lock-keywords-1 ＠＠ -12886,9 +13007,9 ＠＠ ;; (ent-key ent-name ent-file ent-line ;; (arch-key arch-name arch-file arch-line ;; (inst-key inst-name inst-file inst-line inst-comp-name inst-ent-key -;; inst-arch-key inst-conf-key inst-lib-key) +;; inst-arch-key inst-conf-key inst-lib-key inst-path) ;; (lib-name pack-key)) -;; (lib-name pack-key)) +;; mra-key (lib-name pack-key)) (defvar vhdl-config-alist nil "Cache with configurations for each project/directory.") ＠＠ -13054,7 +13175,6 ＠＠ (let* ((ent-name (match-string-no-properties 1)) (ent-key (downcase ent-name)) (ent-entry (aget ent-alist ent-key t)) - (arch-alist (nth 3 ent-entry)) (lib-alist (vhdl-scan-context-clause))) (if (nth 1 ent-entry) (vhdl-warning-when-idle ＠＠ -13064,7 +13184,8 ＠＠ (setq ent-list (cons ent-key ent-list)) (aput 'ent-alist ent-key (list ent-name file-name (vhdl-current-line) - arch-alist lib-alist))))) + (nth 3 ent-entry) (nth 4 ent-entry) + lib-alist))))) ;; scan for architectures (goto-char (point-min)) (while (re-search-forward "^[ \t]*architecture[ \t\n]+\\(\\w+\\)[ \t\n]+of[ \t\n]+\\(\\w+\\)[ \t\n]+is\\>" nil t) ＠＠ -13090,7 +13211,7 ＠＠ (list (or (nth 0 ent-entry) ent-name) (nth 1 ent-entry) (nth 2 ent-entry) (vhdl-sort-alist arch-alist) - (nth 4 ent-entry)))))) + arch-key (nth 5 ent-entry)))))) ;; scan for configurations (goto-char (point-min)) (while (re-search-forward "^[ \t]*configuration[ \t\n]+\\(\\w+\\)[ \t\n]+of[ \t\n]+\\(\\w+\\)[ \t\n]+is\\>" nil t) ＠＠ -13207,41 +13328,55 ＠＠ (beg-of-unit (point)) (end-of-unit (vhdl-get-end-of-unit)) (inst-no 0) - inst-alist) + inst-alist inst-path) ;; scan for contained instantiations (while (and (re-search-forward (concat "^[ \t]*\\(\\w+\\)[ \t\n]*:[ \t\n]*\\(" "\\(\\w+\\)[ \t\n]+\\(--[^\n]*\n[ \t\n]*\\)*\\(generic\\|port\\)[ \t\n]+map\\>\\|" "component[ \t\n]+\\(\\w+\\)\\|" - "\\(\\(entity\\)\\|configuration\\)[ \t\n]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ \t\n]*(\\(\\w+\\))\\)?\\)") end-of-unit t) + "\\(\\(entity\\)\\|configuration\\)[ \t\n]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ \t\n]*(\\(\\w+\\))\\)?\\|" + "\\(\\(for\\|if\\)\\>[^;:]+\\<generate\\>\\|block\\>\\)\\)\\|" + "\\(^[ \t]*end[ \t\n]+\\(generate\\|block\\)\\>\\)") end-of-unit t) (or (not limit-hier-inst-no) (<= (setq inst-no (1+ inst-no)) limit-hier-inst-no))) - (let* ((inst-name (match-string-no-properties 1)) - (inst-key (downcase inst-name)) - (inst-comp-name - (or (match-string-no-properties 3) - (match-string-no-properties 6))) - (inst-ent-key - (or (and (match-string 8) - (vhdl-match-string-downcase 11)) - (and inst-comp-name - (downcase inst-comp-name)))) - (inst-arch-key (vhdl-match-string-downcase 13)) - (inst-conf-key - (and (not (match-string 8)) - (vhdl-match-string-downcase 11))) - (inst-lib-key (vhdl-match-string-downcase 10))) - (goto-char (match-end 1)) - (setq inst-list (cons inst-key inst-list) - inst-ent-list (cons inst-ent-key inst-ent-list)) - (setq inst-alist - (append - inst-alist - (list (list inst-key inst-name file-name - (vhdl-current-line) inst-comp-name - inst-ent-key inst-arch-key - inst-conf-key inst-lib-key)))))) + (cond + ;; block/generate beginning found + ((match-string 14) + (setq inst-path + (cons (match-string-no-properties 1) inst-path))) + ;; block/generate end found + ((match-string 16) + (setq inst-path (cdr inst-path))) + ;; instantiation found + (t + (let* ((inst-name (match-string-no-properties 1)) + (inst-key (downcase inst-name)) + (inst-comp-name + (or (match-string-no-properties 3) + (match-string-no-properties 6))) + (inst-ent-key + (or (and (match-string 8) + (vhdl-match-string-downcase 11)) + (and inst-comp-name + (downcase inst-comp-name)))) + (inst-arch-key (vhdl-match-string-downcase 13)) + (inst-conf-key + (and (not (match-string 8)) + (vhdl-match-string-downcase 11))) + (inst-lib-key (vhdl-match-string-downcase 10))) + (goto-char (match-end 1)) + (setq inst-list (cons inst-key inst-list) + inst-ent-list + (cons inst-ent-key inst-ent-list)) + (setq inst-alist + (append + inst-alist + (list (list inst-key inst-name file-name + (vhdl-current-line) inst-comp-name + inst-ent-key inst-arch-key + inst-conf-key inst-lib-key + (reverse inst-path))))))))) ;; scan for contained configuration specifications (goto-char beg-of-unit) (while (re-search-forward ＠＠ -13291,7 +13426,7 ＠＠ (aput 'ent-alist ent-key (list (nth 0 ent-entry) (nth 1 ent-entry) (nth 2 ent-entry) (vhdl-sort-alist arch-alist) - (nth 4 ent-entry))) + (nth 4 ent-entry) (nth 5 ent-entry))) (when (and limit-hier-inst-no (> inst-no limit-hier-inst-no)) (message "WARNING: Scan limit (hierarchy: instances per architecture) reached in file:\n \"%s\"" file-name) ＠＠ -13484,7 +13619,7 ＠＠ (if (or (nth 1 entry) arch-alist) (aput 'ent-alist ent-key (list (nth 0 entry) (nth 1 entry) (nth 2 entry) - arch-alist (nth 4 entry))) + arch-alist (nth 4 entry) (nth 5 entry))) (adelete 'ent-alist ent-key))) (setq arch-list (cdr arch-list) arch-ent-list (cdr arch-ent-list))) ＠＠ -13548,6 +13683,7 ＠＠ updated)) (setq file-list (cdr file-list))) (setq vhdl-modified-file-list nil) + (vhdl-speedbar-update-current-unit) (when updated (message "Updating hierarchy...done"))))) ;; structure (parenthesised expression means list of such entries) ＠＠ -13607,7 +13743,8 ＠＠ (nth 6 inst-entry) ; from direct instantiation (nth 4 (aget conf-alist (nth 7 inst-entry))) ; from configuration spec. - (caar (nth 3 inst-ent-entry)))) ; random (simplified MRA) + (nth 4 inst-ent-entry) ; MRA + (caar (nth 3 inst-ent-entry)))) ; first alphabetically (setq inst-arch-entry (aget (nth 3 inst-ent-entry) inst-arch-key t)) ;; set library (setq inst-lib-key ＠＠ -13784,7 +13921,7 ＠＠ (progn (load-file file-dir-name) (string< (mapconcat (lambda (a) (format "%3d" (string-to-int a))) - (split-string "3.31.14" "\\.") "") + (split-string "3.33" "\\.") "") (mapconcat (lambda (a) (format "%3d" (string-to-int a))) (split-string vhdl-cache-version "\\.") ""))) ＠＠ -13844,6 +13981,8 ＠＠ (define-key vhdl-speedbar-key-map "_" 'vhdl-speedbar-contract-all) (define-key vhdl-speedbar-key-map "C" 'vhdl-speedbar-port-copy) (define-key vhdl-speedbar-key-map "P" 'vhdl-speedbar-place-component) + (define-key vhdl-speedbar-key-map "F" 'vhdl-speedbar-configuration) + (define-key vhdl-speedbar-key-map "A" 'vhdl-speedbar-select-mra) (define-key vhdl-speedbar-key-map "K" 'vhdl-speedbar-make-design) (define-key vhdl-speedbar-key-map "R" 'vhdl-speedbar-rescan-hierarchy) (define-key vhdl-speedbar-key-map "S" 'vhdl-save-caches) ＠＠ -13885,6 +14024,10 ＠＠ (vhdl-speedbar-check-unit 'subprogram))] ["Place Component" vhdl-speedbar-place-component (vhdl-speedbar-check-unit 'entity)] + ["Generate Configuration" vhdl-speedbar-configuration + (vhdl-speedbar-check-unit 'architecture)] + ["Select as MRA" vhdl-speedbar-select-mra + (vhdl-speedbar-check-unit 'architecture)] ["Make" vhdl-speedbar-make-design (save-excursion (beginning-of-line) (looking-at "[0-9]+: *[[<]"))] ["Generate Makefile" vhdl-speedbar-generate-makefile ＠＠ -14231,7 +14374,8 ＠＠ (ent-entry (aget ent-alist token t)) (arch-alist (nth 3 ent-entry)) (inst-alist (vhdl-get-instantiations token indent)) - (subpack-alist (nth 4 ent-entry)) + (subpack-alist (nth 5 ent-entry)) + (multiple-arch (> (length arch-alist) 1)) arch-entry inst-entry) (if (not (or arch-alist inst-alist subpack-alist)) (speedbar-change-expand-button-char ??) ＠＠ -14254,6 +14398,9 ＠＠ (nth 1 arch-entry) 'vhdl-speedbar-find-file (cons (nth 2 arch-entry) (nth 3 arch-entry)) 'vhdl-speedbar-architecture-face (1+ indent)) + (when (and multiple-arch + (equal (nth 0 arch-entry) (nth 4 ent-entry))) + (end-of-line 0) (insert " (mra)") (forward-char 1)) (setq arch-alist (cdr arch-alist))) ;; insert instantiations (when inst-alist ＠＠ -14486,7 +14633,8 ＠＠ (setq pack-entry (aget pack-alist pack-key t)) (vhdl-speedbar-make-subpack-line (or (nth 0 pack-entry) pack-key) lib-name - (cons (nth 1 pack-entry) (nth 2 pack-entry)) indent) + (cons (nth 1 pack-entry) (nth 2 pack-entry)) + (cons (nth 6 pack-entry) (nth 7 pack-entry)) indent) (setq subpack-alist (cdr subpack-alist))))) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ＠＠ -14708,7 +14856,7 ＠＠ (put-text-property visible-start (point) 'invisible nil))) (defun vhdl-speedbar-make-subpack-line (pack-name lib-name pack-file-marker - depth) + pack-body-file-marker depth) "Insert used package entry." (let ((start (point)) visible-start) ＠＠ -14727,6 +14875,14 ＠＠ (speedbar-make-button start (point) 'vhdl-speedbar-package-face 'speedbar-highlight-face 'vhdl-speedbar-find-file pack-file-marker) + (when (car pack-body-file-marker) + (insert " (") + (setq start (point)) + (insert "body") + (speedbar-make-button + start (point) 'vhdl-speedbar-package-face 'speedbar-highlight-face + 'vhdl-speedbar-find-file pack-body-file-marker) + (insert ")")) (setq start (point)) (insert " (" lib-name ")") (put-text-property (+ 2 start) (1- (point)) 'face ＠＠ -14883,6 +15039,18 ＠＠ (set-text-properties 0 (length string) nil string) string)) +(defun vhdl-speedbar-higher-text () + "Get speedbar-line-text of higher level." + (let (depth string) + (save-excursion + (beginning-of-line) + (looking-at "^\\([0-9]+\\):") + (setq depth (string-to-int (match-string 1))) + (when (re-search-backward (format "^%d: *[[<{][-+?][]>}] \\([^ \n]+\\)" (1- depth)) nil t) + (setq string (match-string 1)) + (set-text-properties 0 (length string) nil string) + string)))) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; Help functions ＠＠ -15007,6 +15175,31 ＠＠ (vhdl-compose-place-component) (select-frame speedbar-frame))) +(defun vhdl-speedbar-configuration () + "Generate configuration for the architecture under the cursor." + (interactive) + (if (not (vhdl-speedbar-check-unit 'architecture)) + (error "ERROR: No architecture under cursor.") + (let ((arch-name (vhdl-speedbar-line-text)) + (ent-name (vhdl-speedbar-higher-text))) + (if (fboundp 'speedbar-select-attached-frame) + (speedbar-select-attached-frame) + (select-frame speedbar-attached-frame)) + (vhdl-compose-configuration ent-name arch-name)))) + +(defun vhdl-speedbar-select-mra () + "Select the architecture under the cursor as MRA." + (interactive) + (if (not (vhdl-speedbar-check-unit 'architecture)) + (error "ERROR: No architecture under cursor.") + (let* ((arch-key (downcase (vhdl-speedbar-line-text))) + (ent-key (downcase (vhdl-speedbar-higher-text))) + (ent-alist (aget vhdl-entity-alist + (or (vhdl-project-p) default-directory) t)) + (ent-entry (aget ent-alist ent-key t))) + (setcar (cddr (cddr ent-entry)) arch-key) ; (nth 4 ent-entry) + (speedbar-refresh)))) + (defun vhdl-speedbar-make-design () "Make (compile) design unit or directory/project under the cursor." (interactive) ＠＠ -15041,6 +15234,10 ＠＠ (memq (get-text-property (match-end 0) 'face) '(vhdl-speedbar-entity-face vhdl-speedbar-entity-selected-face))) + ((eq design-unit 'architecture) + (memq (get-text-property (match-end 0) 'face) + '(vhdl-speedbar-architecture-face + vhdl-speedbar-architecture-selected-face))) ((eq design-unit 'subprogram) (eq (get-text-property (match-end 0) 'face) 'vhdl-speedbar-subprogram-face)) ＠＠ -15254,7 +15451,7 ＠＠ (vhdl-insert-keyword "END ") (unless (vhdl-standard-p '87) (vhdl-insert-keyword "ARCHITECTURE ")) (insert arch-name ";\n\n") - ;; insert footer + ;; insert footer and save (if (and vhdl-compose-include-header (not (equal vhdl-file-footer ""))) (vhdl-template-footer) (vhdl-comment-display-line) (insert "\n")) ＠＠ -15388,7 +15585,8 ＠＠ (vhdl-port-copy)))) (vhdl-port-flatten t) (setq generic-alist (nth 1 vhdl-port-list) - port-alist (nth 2 vhdl-port-list)) + port-alist (nth 2 vhdl-port-list) + vhdl-port-list nil) (setq constant-alist nil signal-alist nil) (when has-generic ＠＠ -15716,6 +15914,178 ＠＠ (message "Generating components package \"%s\"...done\n File created: \"%s\"" pack-name pack-file-name))) +(defun vhdl-compose-configuration-architecture (ent-name arch-name inst-alist + &optional insert-conf) + "Generate block configuration for architecture." + (let ((margin (current-indentation)) + (beg (save-excursion (beginning-of-line) (point))) + ent-entry inst-entry inst-path inst-prev-path cons-key tmp-alist) + ;; insert block configuration (for architecture) + (vhdl-insert-keyword "FOR ") (insert arch-name "\n") + (setq margin (+ margin vhdl-basic-offset)) + ;; process all instances + (while inst-alist + (setq inst-entry (car inst-alist)) + ;; is component? + (when (nth 4 inst-entry) + (setq insert-conf t) + (setq inst-path (nth 9 inst-entry)) + ;; skip common path with previous instance + (while (and inst-path (equal (car inst-path) (car inst-prev-path))) + (setq inst-path (cdr inst-path) + inst-prev-path (cdr inst-prev-path))) + ;; insert block configuration end (for previous block/generate) + (while inst-prev-path + (setq margin (- margin vhdl-basic-offset)) + (indent-to margin) + (vhdl-insert-keyword "END FOR;\n") + (setq inst-prev-path (cdr inst-prev-path))) + ;; insert block configuration beginning (for current block/generate) + (indent-to margin) + (while inst-path + (setq margin (+ margin vhdl-basic-offset)) + (vhdl-insert-keyword "FOR ") + (insert (car inst-path) "\n") + (indent-to margin) + (setq inst-path (cdr inst-path))) + ;; insert component configuration beginning + (vhdl-insert-keyword "FOR ") + (insert (nth 1 inst-entry) " : " (nth 4 inst-entry) "\n") + ;; find subconfiguration + (setq conf-key (nth 7 inst-entry)) + (setq tmp-alist conf-alist) + ;; use first configuration found for instance's entity + (while (and tmp-alist (null conf-key)) + (when (equal (nth 5 inst-entry) (nth 4 (car tmp-alist))) + (setq conf-key (nth 0 (car tmp-alist)))) + (setq tmp-alist (cdr tmp-alist))) + (setq conf-entry (aget conf-alist conf-key t)) + ;; insert binding indication ... + ;; ... with subconfiguration (if exists) + (if (and vhdl-compose-configuration-use-subconfiguration conf-entry) + (progn + (indent-to (+ margin vhdl-basic-offset)) + (vhdl-insert-keyword "USE CONFIGURATION ") + (insert (vhdl-work-library) "." (nth 0 conf-entry)) + (insert ";\n")) + ;; ... with entity (if exists) + (setq ent-entry (aget ent-alist (nth 5 inst-entry) t)) + (when ent-entry + (indent-to (+ margin vhdl-basic-offset)) + (vhdl-insert-keyword "USE ENTITY ") + (insert (vhdl-work-library) "." (nth 0 ent-entry)) + ;; insert architecture name (if architecture exists) + (when (nth 3 ent-entry) + (setq arch-name + ;; choose architecture name a) from configuration, + ;; b) from mra, or c) from first architecture + (or (nth 0 (aget (nth 3 ent-entry) + (or (nth 6 inst-entry) + (nth 4 ent-entry)) t)) + (nth 1 (car (nth 3 ent-entry))))) + (insert "(" arch-name ")")) + (insert ";\n") + ;; insert block configuration (for architecture of subcomponent) + (when (and vhdl-compose-configuration-hierarchical + (nth 3 ent-entry)) + (indent-to (+ margin vhdl-basic-offset)) + (vhdl-compose-configuration-architecture + (nth 0 ent-entry) arch-name + (nth 3 (aget (nth 3 ent-entry) (downcase arch-name) t)))))) + ;; insert component configuration end + (indent-to margin) + (vhdl-insert-keyword "END FOR;\n") + (setq inst-prev-path (nth 9 inst-entry))) + (setq inst-alist (cdr inst-alist))) + ;; insert block configuration end (for block/generate) + (while inst-prev-path + (setq margin (- margin vhdl-basic-offset)) + (indent-to margin) + (vhdl-insert-keyword "END FOR;\n") + (setq inst-prev-path (cdr inst-prev-path))) + (indent-to (- margin vhdl-basic-offset)) + ;; insert block configuration end or remove beginning (for architecture) + (if insert-conf + (vhdl-insert-keyword "END FOR;\n") + (delete-region beg (point))))) + +(defun vhdl-compose-configuration (&optional ent-name arch-name) + "Generate configuration declaration." + (interactive) + (vhdl-require-hierarchy-info) + (let ((ent-alist (aget vhdl-entity-alist + (or (vhdl-project-p) default-directory) t)) + (conf-alist (aget vhdl-config-alist + (or (vhdl-project-p) default-directory) t)) + (from-speedbar ent-name) + inst-alist conf-name conf-file-name pos) + (vhdl-prepare-search-2 + ;; get entity and architecture name + (unless ent-name + (save-excursion + (unless (and (re-search-backward "^\\(architecture\\s-+\\(\\w+\\)\\s-+of\\s-+\\(\\w+\\)\\|end\\)\\>" nil t) + (not (equal "END" (upcase (match-string 1)))) + (setq ent-name (match-string-no-properties 3)) + (setq arch-name (match-string-no-properties 2))) + (error "ERROR: Not within an architecture")))) + (setq conf-name (vhdl-replace-string + vhdl-compose-configuration-name + (concat ent-name " " arch-name))) + (setq inst-alist + (nth 3 (aget (nth 3 (aget ent-alist (downcase ent-name) t)) + (downcase arch-name) t)))) + (message "Generating configuration \"%s\"..." conf-name) + (if vhdl-compose-configuration-create-file + ;; open configuration file + (progn + (setq conf-file-name + (concat (vhdl-replace-string vhdl-configuration-file-name + conf-name t) + "." (file-name-extension (buffer-file-name)))) + (when (and (file-exists-p conf-file-name) + (not (y-or-n-p (concat "File \"" conf-file-name + "\" exists; overwrite? ")))) + (error "ERROR: Creating configuration...aborted")) + (find-file conf-file-name) + (erase-buffer) + (set-buffer-modified-p nil) + ;; insert header + (if vhdl-compose-include-header + (progn (vhdl-template-header + (concat "Configuration declaration for design \"" + ent-name "(" arch-name ")\"")) + (goto-char (point-max))) + (vhdl-comment-display-line) (insert "\n\n"))) + ;; goto end of architecture + (unless from-speedbar + (re-search-forward "^end\\>" nil) + (end-of-line) (insert "\n\n") + (vhdl-comment-display-line) (insert "\n\n"))) + ;; insert library clause + (setq pos (point)) + (vhdl-template-standard-package (vhdl-work-library) nil) + (when (/= pos (point)) + (insert "\n\n")) + ;; insert configuration + (vhdl-insert-keyword "CONFIGURATION ") (insert conf-name) + (vhdl-insert-keyword " OF ") (insert ent-name) + (vhdl-insert-keyword " IS\n") + (indent-to vhdl-basic-offset) + ;; insert block configuration (for architecture) + (vhdl-compose-configuration-architecture ent-name arch-name inst-alist t) + (vhdl-insert-keyword "END ") (insert conf-name ";") + (when conf-file-name + ;; insert footer and save + (insert "\n\n") + (if (and vhdl-compose-include-header (not (equal vhdl-file-footer ""))) + (vhdl-template-footer) + (vhdl-comment-display-line) (insert "\n")) + (save-buffer)) + (message + (concat (format "Generating configuration \"%s\"...done" conf-name) + (and conf-file-name + (format "\n File created: \"%s\"" conf-file-name)))))) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; Compilation / Makefile generation ＠＠ -15991,7 +16361,7 ＠＠ (setq ent-file-name (file-relative-name (nth 2 ent-entry) compile-directory) arch-alist (nth 4 ent-entry) - lib-alist (nth 5 ent-entry) + lib-alist (nth 6 ent-entry) rule (aget rule-alist ent-file-name) target-list (nth 0 rule) depend-list (nth 1 rule) ＠＠ -16261,7 +16631,8 ＠＠ (insert " \\\n\t\t$(UNIT-" work-library "-" (car second-list) ")") (setq second-list (cdr second-list))) (while subcomp-list - (when (assoc (car subcomp-list) unit-list) + (when (and (assoc (car subcomp-list) unit-list) + (not (equal unit-key (car subcomp-list)))) (insert " \\\n\t\t" (car subcomp-list))) (setq subcomp-list (cdr subcomp-list))) (insert "\n") ＠＠ -16366,8 +16737,10 ＠＠ 'vhdl-upper-case-enum-values 'vhdl-upper-case-constants 'vhdl-use-direct-instantiation + 'vhdl-compose-configuration-name 'vhdl-entity-file-name 'vhdl-architecture-file-name + 'vhdl-configuration-file-name 'vhdl-package-file-name 'vhdl-file-name-case 'vhdl-electric-keywords ＠＠ -16413,6 +16786,9 ＠＠ 'vhdl-testbench-entity-file-name 'vhdl-testbench-architecture-file-name 'vhdl-compose-create-files + 'vhdl-compose-configuration-create-file + 'vhdl-compose-configuration-hierarchical + 'vhdl-compose-configuration-use-subconfiguration 'vhdl-compose-include-header 'vhdl-compose-architecture-name 'vhdl-components-package-name ＠＠ -16475,106 +16851,34 ＠＠ (defconst vhdl-doc-release-notes nil "\ -Release Notes for VHDL Mode 3.32 +Release Notes for VHDL Mode 3.33 ================================ - New Features - - Enhanced Features - User Options - - Remarks New Features ------------ - -STRUCTURAL COMPOSITION: - - Enables simple structural composition similar to graphical editors. - Simplifies the creation of higher design levels where subcomponents - are simply sticked together: - 1. Create a skeleton for a new component - 2. Place subcomponents in it directly from the hierarchy browser - 3. Automatically connect all subcomponents and create the ports - for the new component (based on names of actual ports) - - Automatic generation of a components package (package containing - component declarations for all entities). - - Find more information in the online documentation (`C-c C-h'). - -PORT TRANSLATION: - - Reverse direction of ports (useful for testbenches). - -SUBPROGRAM TRANSLATION: - - Copy/paste of subprogram interfaces (similar to port translation). - -CODE FILLING: - - Condense code using code-sensitive block filling. - -CODE STATISTICS: - - Calculate number of code lines and statements in a buffer. - - -Enhanced Features ------------------ - -TESTBENCH GENERATION: - - Enhanced templates and user option default values. - -Emacs 21 compatibility/enhancements: - - `lazy-lock-mode' is not used anymore (built-in `jit-lock-mode' is faster). -And many other minor fixes and enhancements. +CONFIGURATION DECLARATION GENERATION: + - Automatic generation of a configuration declaration for a design. + (See documentation (`C-c C-h') in section on STRUCTURAL COMPOSITION.) User Options ------------ -`vhdl-project-file-name': (enhanced) - Include user name in project setup file name. -`vhdl-speedbar-cache-file-name': (enhanced, changed default) - Include user name in cache file name. -`vhdl-default-library': (new) - Default working library if no project is active. -`vhdl-architecture-file-name': (new) - Specify how the architecture file name is obtained. -`vhdl-package-file-name': (new) - Specify how the package file name is obtained. -`vhdl-file-name-case': (new) - Allows to change case when deriving file names. -`vhdl-compose-create-files': (new) - Specify whether new files should be created for a new component. -`vhdl-compose-include-header': (new) - Specify whether a header is included in a new component's file. -`vhdl-compose-architecture-name': (new) - Specify how a new component's architecture name is obtained. -`vhdl-components-package-name': (new) - Specify how the name for the components package is obtained. -`vhdl-use-components-package': (new) - Specify whether component declarations go in a components package. -`vhdl-use-direct-instantiation': (new) - Specify whether to use VHDL'93 direct component instantiation. -`vhdl-instance-name': (changed default) - Allows insertion of a running number to generate unique instance names. -`vhdl-testbench-entity-header', `vhdl-testbench-architecture-header':(obsolete) - Headers are now automatically derived from the standard header. -`vhdl-testbench-include-header': (new) - Specify whether a header is included in testbench files. -`vhdl-testbench-declaration', `vhdl-testbench-statements': (changed default) - Non-empty default values for more complete testbench templates. -`vhdl-testbench-entity-file-name': (new) - Specify how the testbench entity file name is obtained. -`vhdl-testbench-architecture-file-name': (new) - Specify how the testbench architecture file name is obtained. - - -Remarks -------- - -- Changed key binding for `vhdl-comment-uncomment-region': `C-c c' - (`C-c C-c ...' is now used for structural composition). - -- Automatic buffer highlighting (font-lock) is now controlled by option - `global-font-lock-mode' in GNU Emacs (`font-lock-auto-fontify' in XEmacs). - \(Important: You MUST customize this option in order to turn automatic - buffer highlighting on.) +`vhdl-configuration-file-name': (new) + Specify how the configuration file name is obtained. +`vhdl-compose-configuration-name': (new) + Specify how the configuration name is optained. +`vhdl-compose-configuration-create-file': (new) + Specify whether a new file should be created for a configuration. +`vhdl-compose-configuration-hierarchical': (new) + Specify whether hierarchical configurations should be created. +`vhdl-compose-configuration-use-subconfiguration': (new) + Specify whether subconfigurations should be used inside configurations. ")